[time-nuts] Question concerning failure and value of HP 5371A
hmurray at suespammers.org
Mon Oct 17 06:22:33 EDT 2005
> I would like to experiment with 1 ns or 2 ns pulses and gates capable
> to count such pulses, meaning with bin. counters able to work with
> 250 MHz or up to 500 MHz clock in signal. That speed just for that 2
> primary elements of a (high speed) counter. Am I dreaming? I like it.
You should probably start looking at the details in the data sheets. FPGAs
are complicated. Expect to read them several times until the ideas sink in.
I'll say more off list if you want.
Xilinx and Altera are the major players. I'm not familiar with Altera's
parts. Both have free software.
Xilinx has two general families. Spartan is low cost with modest
performance. Virtex is bleeding edge, higher cost for higher performance.
Spartan 3 and Virtex 4 are the parts to look at.
I'm pretty sure the Spartan 3 will run at 250 MHz. The DLL input only runs
at 280 MHz but the output can go up to 334 MHz. You might get close(er) to
500 MHz for small chunks of logic. I'm not sure how. I couldn't find the
specs for the clock distribution tree.
Virtex 4 is faster. DCM runs at 400-500 MHz (depending on speed grade of the
chip) so you can probably run large chunks of logic at that speed. Xilinx
has an eval board for $500 - looks good at a quick glance. I haven't used it.
It's got a pair of SMA connectors for a differential clock input.
Check out the others too.
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