[time-nuts] DC Voltage Ramp?

Magnus Danielson cfmd at bredband.net
Sun Sep 4 19:33:44 EDT 2005

From: "Tom Van Baak" <tvb at leapsecond.com>
Subject: Re: [time-nuts] DC Voltage Ramp?
Date: Sun, 4 Sep 2005 15:44:20 -0700
Message-ID: <001101c5b1a2$31cf1380$1c12f204 at computer>

> > Hi Tom & Robert:
> > 
> > I think what this is saying is that if the control voltage to the OCXO 
> > is fixed, then during the 10,000 (or more) seconds needed for GPS the 
> > OCXO has drifted about 5E-11/day * 10,000/86400 = 6E-12 seconds which 
> > exceeds what we are trying to accomplish.
> > 
> > BUT, if instead of using a fixed control voltage, a Ramp is used then 
> > this will not happen.  Now instead of using GPS to control a fixed 
> > voltage it's used to control the slope of the ramp.
> > 
> > What am I missing?
> Brooke,
> I'm not up on my PLL theory but if GPS is used with
> a PLL the DAC will change to keep the loop locked.
> And if you plot the DAC voltage you will see wiggles
> over the short-term (seconds to hours) and a ramp
> in the long-term (days to weeks). The size of the
> wiggles or the smoothness of the ramp varies greatly
> from oscillator to oscillator.

Notice that the wiggles you see on the DAC control is just those that makes it
through the loop filter. If you monitor the phase detector (usually a time-
interval counter for these applications) you will see even more wiggeling.

> So the question for a PLL expert is - if knowing that
> there is a ramp trend over a time frame of days or
> weeks; can that knowledge somehow help the PLL
> as it tries to close the loop on a second by second
> or minute by minute time frame? My guess is no.

I would say that you can. It all depends on the degree of your PLL.
If we are talking about clear-cut PLLs and is not going into the fancy stuff of
Kalman filters or particle filters or anything near it, this will be pretty

For a first degree PLL (no loop filter, only loop gain), you will have
frequency lock, but a stable phase error is requried to through the loop gain
acheive the frequency error correction needed for the difference between the
signal and the unmodulated oscillator.

For a second degree PLL (loop filter has an integrator in parallel with a gain
path), the phase error can be worked up into the integrator, so that the stable
phase will adjust, but it fails to handle a phase ramp/frequency shift without
lagging behind.

For a third degree PLL (loop filter has a gain path, a single integrator path
and a double integrator path all summed up), the phase ramp/frequency shift can
be worked into the second integrator, but it faisl to handle a phase parabolid/
frequency ramp without lagging behind.

A forth degre PLL can handle the frequency ramp without error.

For a PLL of a degree which tracks one of these signals with error, the signal
type next up the ladder it will fail to track and will eventually loose lock.

Whenever you see a phase step, phase ramp/frequency step or phase parabol/
frequency ramp/drift step begin, a PLL able to work it out will wiggle around
its target, but will then work out the errors as it integrate in the new

You can get what seems like the same performance using a lesser degree PLL,
by choosing a fancier phase detector which also does frequency detection, but
in reality you have just moved the integrator pole from the loop filter over to
the detector. Having a simple detector like a 4-quadrant multiplier or a
fullblown time-interval counter doesn't really change much, just the way we

Anyway, so knowing that we have a phase ramp or even frequency ramp we can have
use for by choosing the degree of the PLL and then it will be able to cope with
it. This is all known in traditional PLL terms and is really just an exercise
using linear control loop theory applied to the field of PLLs. Gardners book is
certainly a good reference to start with, unless you want the fancy looking
Best book, which have its points but is not the best IMHO.

> When the short-term frequency wiggles around
> parts in 10^12th to parts in 10^11th a gradual
> long-term average trend of 5e-10 per day is so
> far below the noise that it is of no use to the
> PLL which must act with a short time constant.
> As an example, you can find a nice 10811 that
> has a drift rate of 5e-10 / day. Using your math
> that comes to 50e-11 / 24 hours or about 2e-11
> per hour. But take a look at a typical 10-minute
> frequency strip-chart of a 10811 oscillator:
> http://www.leapsecond.com/museum/hp10811/log14693v.gif
> You can see that in just the space of minutes
> it wanders around more than an hour's worth
> of drift. Look at some of the other plots in that
> folder too.
> The point is, a PLL must react to phase and
> frequency changes in real-time. In most cases
> the normal minute-to-minute fluctuations in a
> warmed-up and well-aged quartz oscillator are
> much larger than the extrapolated contribution
> of the long-term drift rate for the same interval,
> even if the drift rate were constant.

Indeed. The resulting phase-noise is a blend between the oscillators and the
reference signals. This blend is using the lowpass part of the reference and
the highpass part of the oscillator crossed over at the PLLs bandwidth. The
degree of the PLL decides what the slopes of the lowpass and highpass becomes.
While this was an exercise in the frequency domain, it surely can be translated
into the time-domain of Allan deviation or its modified form. The trick is
really to choose the bandwidth/tau of the PLL such that the optimum phase noise
is acheived and some thought also needs to go into the ability to maintain

If you do Kalman filtering, it will change the tau as it learns the errors and
will perform better than any PLL since it will effectively adjust the tau to
the situation rather than some engineering decission had it a few years back.

If you do fancy PLL stuff, you can aid the PLL tracking with external sensors,
so that temperature measurements, accelerometers etc. can be used to feed
correction signals such that the PLL loop does not have to track it all in
by itself. The gain of such a solution is that a wider range of PLL parameters
may be chosen.

So, there is alot more to do then just to "lock it up". The performance you get
certainly can be improved as a result.


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