[time-nuts] Interfacing a 8dBm sine output of an OCXO to a digital logic standard
phk at phk.freebsd.dk
Fri Sep 16 10:43:26 EDT 2005
In message <email@example.com>, David Forbes writes:
>>My very stable OCXO output a 8dBm (50ohm) sine wave. How is this signal
>>converted/interfaced to a logic standard (e.g. LVDS)?
The best way to do it is actually with 1:1 PLL.
In modern computers the synchronous RAM requires clock signals which
have very tight specs on delay and jitter and the only way this is
possible in practice is by using 1:1 PLL's as "zero delay buffers".
See for instance:
ICS has many interesting clock chips which can be used for other
uses than what they were designed. Worth a browse.
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