[time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard

David Forbes dforbes at dakotacom.net
Fri Sep 16 12:25:53 EDT 2005

David Kirkby wrote:
> Poul-Henning Kamp wrote:
>> In message <MGEKKFGEAIKJOOPJPGIKCEAMFMAA.richard at karlquist.com>, 
>> "Richard \(Ric
>> k\) Karlquist \(N6RK\)" writes:
>>>>     http://www.icst.com/datasheets/ics2305.pdf
>>>> ICS has many interesting clock chips which can be used for other
>>>> uses than what they were designed.  Worth a browse.
>>>> -- 
>>>> Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
>>> This chip has 200 ps of jitter!  There is no way you would
>>> want to use this with an OCXO.
>> Be aware they don't mean the same with "jitter" as you do: they
>> include production tolerances, so the 200ps is the worst case jitter
>> measured between two output pins on a large lot of chips, not the
>> jitter you would measure on a single output on a single chip.
> What you are describing sounds more like the 700ps "Device to Device Skew".

I used one of those chips about 5 years ago on a CPU board, and it did 
have about 100ps of jitter. It was horrible as a clock source. I think 
it was suffering a bit from being on a CPU board, though, with all the 
digital switching noise around it.

Later versions were better, but still not very good by analog PLL 

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