[time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
newell at cei.net
Fri Sep 16 12:35:22 EDT 2005
At 09:43 AM 9/16/2005 , Poul-Henning Kamp wrote:
>In modern computers the synchronous RAM requires clock signals which
>have very tight specs on delay and jitter and the only way this is
>possible in practice is by using 1:1 PLL's as "zero delay buffers".
>See for instance:
>ICS has many interesting clock chips which can be used for other
>uses than what they were designed. Worth a browse.
I used one to multiple my 10MHz OCXO reference to 80MHz. The idea was to
replace the little 80MHz "clock box" oscillator in a Sun IPX with a
precision clock source. Didn't work. I guess the IPX doesn't derive its
100Hz ticker from the CPU clock.
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