[time-nuts] IC for 1 PPS Output
SAIDJACK at aol.com
SAIDJACK at aol.com
Fri Apr 7 14:00:03 EDT 2006
Paralleling CMOS inverters to drive time critical signals is not a good idea
because the inverters have skews between them, even if they are on the same
chip (die).
The skew for an improved version of the 74AC04 part (the 74LVC04) is
specified as up to 1.5ns!
Interesting enough, this parameter is wrong in the Philips datasheet, they
say 1.5ps (impossible, since the difference in lead size of a couple of mm
would already cause >>1.5ps skew). I confirmed with Philips that it's supposed
to be nanoseconds, not picoseconds:
_http://www.semiconductors.philips.com/acrobat_download/datasheets/74LVC04A_6.
pdf_
(http://www.semiconductors.philips.com/acrobat_download/datasheets/74LVC04A_6.pdf)
This 1.5ns skew would cause all sorts of issues on the edges since the
rise/fall time I measure on these parts is <1ns, so theoretically you could have
one output drive high, and the adjacent one drive low for up to 0.5ns causing
a short circuit over the termination resistors.
It's better to use a single, faster, 5V compatible, LVC logic driving
through a single series termination resistor. This series termination resistor is
adjusted so that an open-ended cable shows a perfect square wave on its end.
The cable has to be about 2-3 feet long going into a >1MOhm or higher fast
oscilloscope or FET probe input.
BTW: the value of the series terminator doesen't matter when the cable is
50Ohm end terminated since there will be no reflection from the end of the
cable. Thus the value of the series termination resistor will determine the
peak-to-peak voltage into a 50Ohm end terminated cable. The gate needs to be
choosen so that it can drive down to 50 Ohms without damage of course.
There is one advantage to using multiple gates: they will share the energy
of ESD pulses, or external DC voltages applied to the connector, and thus have
a higher survivability under stress conditions.
bye,
SJ
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