[time-nuts] IC for 1 PPS Output

Hal Murray hmurray at suespammers.org
Fri Apr 7 16:17:09 EDT 2006

> When I use 3 x 47 Ohm resistors and 3 gates the rise time seems about
> the same, but the voltage into a 50 Ohm load increases from 2.5 V p-p
> to  3.6 v p-p, so I tend to agree that's the way to go.

One thing was missing from your original question.  What sort of receiver are 
you going to use?  Do you want an input to more digital logic or are you 
going into lab gear with an adjustable trigger threshold?

If you are trying to preserve timing on a cable going from box to box, 
differential signaling avoids (most of) the noise due to ground not being the 
same on both boxes.  LVDS is the modern version.  26LS31/32 and friends 
(RS-422) is the old low-tech stuff available in DIPs.

Normal ECL/PECL chips are happy with 50 ohm loads.  You might not like the DC 
offset if you want to receive it with something else.  It should be easy to 
AC couple if you are sending clock signals with a 50% duty cycle.  (You may 
need to bias the receiver.)

You might find good chips intended for use as clock buffers.  They probably 
won't come in DIPs so wiring them up as a hack will be a pain.  They usually 
come with good data sheets and app-notes.

I'm pretty sure I've seen an app-note saying it was OK to parallel drivers in 
the same package.  I wonder what the technology was.

One disadvantage of the op-amp or video buffer approach is that analog chips 
often need supply voltages that are not common on digital logic.  They are 
often slew rate limited for large signal swings which doesn't give a great 
rise time.

I'm slightly surprised there isn't a stock answer to this question.  Seems 
like it should be in a FAQ someplace.  If I was sending in an order to 
Digikey, I'd probably order a few of the old TTL 74128s just so I could put 
them on a scope.  It's probably worth using as a straw man.

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