[time-nuts] TIC232 Detailed Operation

[Richard H McCorkle]

Here is a detailed description of the operation of the 
Simple Time Interval Counter.

 1. A sample counter is loaded with the selected number 
     of samples
 2. TMR1 is enabled, interrupts are enabled, GPS 1PPS 
     hasn't arrived yet so the 4046 output is low, TMR1G 
     is low, and TMR1 isn't counting. 
 3. GPS 1PPS goes high and triggers the 4046 phase detector 
     causing it's output to go high. 
 4. The high from the 4046 takes the TMR1G gate pin high 
     enabling TMR1 to count. 
 5. TMR1 begins counting the 16 MHz XO 
 6. Whenever TMR1 overflows, the TMR1IF flag is set. 
     When the background routine sees the TMR1IF flag 
     set, it increments an overflow counter that keeps track 
     of the number of overflows, and resets the TMR1IF flag.
 7. TMR1 continues to count the 16 MHz XO without 
     interruption since TMR1 is set for async mode. 
 8. When DUT 1PPS goes high, the 4046 output goes low.
 9. When the 4046 output goes low TMR1 stops counting.
10. The falling edge of the 4046 output interrupts the processor 
      starting the ISR
11. The ISR decrements a sample counter and sees if the 
      selected number of samples has been accumulated. 
      If not, it just returns from interrupt and goes back to step 1 
      and waits for the next GPS 1PPS to restart TMR1.
12. Once the selected number of samples has accumulated, the 
      ISR disables the async counter, reads the TMR1 value into the 
      low 16-bits of a 32-bit register, clears the TMR1 registers, and 
      enables the async counter so the next TMR1G can restart it. 
13. The ISR checks if a TMR1 overflow has occurred, increments 
      the overflow counter and clears TMR1IF if it has. (Just in case 
      an overflow happened and the interrupt came in before the 
      background routine could clear it.)
14. The ISR reads the 16-bit overflow counter into the high 16-bits 
      of the 32-bit register and clears it. 
15. The 32-bit register is converted to 10-digit BCD, printed, and cleared.
16. The sample time counter is reloaded, and the ISR returns.

For a 1-second sample, the LSB of the count printed represents the 
clock period (1/XO Speed) or 62.5ns for a 16 MHz XO. For multiple 
samples accumulated the LSB of the count represents the clock 
period / # of samples ((1/XO Speed)/# of Samples). Since the GPS 
1PPS starts each sample, the sample time in seconds equals the 
number of samples accumulated, and the update rate at which the 
accumulator is printed. 

By selecting a known sample time for the XO speed used, the LSB 
of the displayed data has a known time value. By default the 60-second 
sample period gives an LSB of 1.04ns. No dividing by the sample time 
or other scaling needs to be done to the count displayed, it is already 
scaled by the XO speed and sample time used. By changing the 
sample time to calibrate the reading, the count can be scaled to read 
directly. For instance, accumulating 625 samples with a 16 MHz XO 
speed would result in a count with an LSB of 100 ps. Since the Simple 
Time Interval Counter only goes to 256 samples, averaging 250 samples 
would give an LSB of 0.25ns and an output count displayed once every 
4:10. An LSB value of exactly 1ns would require 62.5 seconds per 
update. Because partial sample times aren't allowed, a 60-second 
value was chosen as default giving an LSB of 1.04ns and an output 
count displayed once per minute.

For LSB's that are not calibrated, like the default 1.04ns, a conversion 
to actual time can be done in a spreadsheet or AD calculator by 
multiplying the count output from the TIC by the actual LSB value, 
and the corrected values used in data analysis. 

I hope this helps clear up any misconceptions on the operation of 
the Simple Time Interval Counter.

Enjoy!
Richard