[time-nuts] Some More questions

Hal Murray hmurray at suespammers.org
Thu Jan 19 04:39:58 EST 2006

> Then, I am not sure all GPS receivers actually use their internal
> crystal oscillator in a PLL as the timebase. I have read that some
> work  by removing or adding pulses in a discrete fashion rather than
> phase  locking, and this offers significant jitter, making the 1 PPS
> only  useable to phase lock a reference oscillator with a very long
> integration period to eliminate the jitter.

> Now, I can't find the article describing that technique, so it may
> have  been old news. 

It's a reasonably common trick in the digital world.  Direct Digital 

Analog Devices makes chips that do it all.  They have good app notes and data 

If you have a clock running at X and you want Y when Y is (much) smaller than 
X, just make a big adder and add a magic number each clock tick.  Think of 
the decimal (binary) point at the left end of the adder.  So if you start 
with 8 MHz and you want 1 MHz, just add 001 (binary) to a 3 bit register each 
cycle.  The top bit is the output.

If the ratio doesn't come out even, you can get arbitrarily close by adding 
more bits.  You are adding low bits on the right of the adder.

If you want a sine wave, take the top N bits and feed them to a table lookup 
ROM and feed that to a DAC.

The output frequency is solid - maybe not exactly what you want but you can 
compute it from the constant you add, the main clock frequency, and the 
number of bits in the adder.

The output clock ticks will be on the closest main clock edge.  That leaves 
you with a 1/2 cycle of jitter.  In many applications that's not a big deal.

Somebody mentioned a sawtooth jitter pattern.  That's what I would expect 
from this sort of clock if the target frequency is very close but off 
slightly.  Say you want 1 HZ but your crystal is running a tiny bit fast.  
Every now and then it will insert an extra cycle to slow down the output.  
I'll bet that turns into a sawtooth of phase error if you compare it to a 
good reference clock.  The phase error will build up to 1/2 cycle then it 
will slip to -1/2 cycle and start building up again.

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