[time-nuts] PLL Phase Noise vs. Divider Jitter

Stephan Sandenbergh stephan at rrsg.ee.uct.ac.za
Sat Jul 8 11:34:36 EDT 2006


Hi All,

In the previous thread, "HP 58540A Phase Noise Improvements", Matt Ettus
noted the following: 

The jitter that is added by a divider would most probably pose a greater
limit to the phase noise of the PLL than that of the specific OCXO used.  

Now my question: How can one divide a digital signal without using jittery
flip-flop based counters (either discrete of those found in FPGAs)? The
first thing that springs to mind is that of the analog pulse stretchers
which were discussed last month. This may provide one with lower jitter but
it would most probably increase the longer term instabilities due to
temperature and power supply variations. What are there other alternatives?

Regards,

Stephan.




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