[time-nuts] PLL Phase Noise vs. Divider Jitter

[Magnus Danielson]

From: "Stephan Sandenbergh" <stephan at rrsg.ee.uct.ac.za>
Subject: [time-nuts] PLL Phase Noise vs. Divider Jitter
Date: Sat, 8 Jul 2006 17:34:36 +0200
Message-ID: <000001c6a2a4$0546f370$401c9e89 at Stephan>

> Hi All,

Stephan,

You keep on posing various questions! Keep it up! ;O)

> In the previous thread, "HP 58540A Phase Noise Improvements", Matt Ettus
> noted the following: 
> 
> The jitter that is added by a divider would most probably pose a greater
> limit to the phase noise of the PLL than that of the specific OCXO used.  

This sounds a little strange. Most of the jitter will be filtered out by the
PLL loop filter. Since we discuss OCXO we are discussing fairly moderate
frequencies (5-20 MHz) and acheiving low jitter dividers should not be a
problem.

> Now my question: How can one divide a digital signal without using jittery
> flip-flop based counters (either discrete of those found in FPGAs)? The
> first thing that springs to mind is that of the analog pulse stretchers
> which were discussed last month. This may provide one with lower jitter but
> it would most probably increase the longer term instabilities due to
> temperature and power supply variations. What are there other alternatives?

One trick of trade is to user a cheap divider to run the division state, and
then use a DFF clocked by the input signal to sample the state-bit from the
divider and then the jitter addition will only be from that DFF. You can spend
the extra care and money on that DFF only.

Cheers,
Magnus