[time-nuts] Conditioning clock signal paths

Magnus Danielson cfmd at bredband.net
Wed Jun 28 08:59:41 EDT 2006

From: "Poul-Henning Kamp" <phk at phk.freebsd.dk>
Subject: Re: [time-nuts] Conditioning clock signal paths
Date: Wed, 28 Jun 2006 12:37:29 +0000
Message-ID: <21192.1151498249 at critter.freebsd.dk>

> In message <003f01c69a9d$62158bc0$401c9e89 at Stephan>, "Stephan Sandenbergh" writ
> es:
> >Now for the paradox: Do you filter your digital signal to lower the noise
> >bandwidth? Or do you want a high as possible rise time (slew rate) to get
> >the best PSSR?
> The advantage to digital signals (ie: square-oid signals) as opposed
> to analog signals (ie: sines) is that the slew-rate is higher.  That
> means that it is less important at which precise voltage the
> L->H or H->L transistion happens and therefore you don't need
> precise analog reference voltages in your logic circuits.
> The low slewrate of a sine would mean that even small changes
> in threshold voltage would come out as large jitters in time.

Worse yet, the broadband noise will make sure to add jitter. There is a very
direct relationship between slew-rate, noise and jitter. This jitter will limit
the time-resolution of the measurement. Slew-rate is in a very direct
relation to amplitude and frequency. Slow changes in offset (due to power and
temperature) will certainly contribute to wander effects.


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