[time-nuts] 5 MHz Frequency Doubler (Dr Bruce Griffiths)

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Oct 27 23:51:28 EDT 2006

Christopher Hoover wrote:
> Dr Bruce Griffiths wrote:
>> The design is probably a pair of low noise n channel JFETs 
>> configured as a push push doubler.
>> Inputs driven in antiphase so that each FET conducts ffor 
>> opposite 1/2 cycles with the 2 FET drains connected in parallel.
>> A bypassed trimpot connected between the FET sources being 
>> used to compensate for FET mismatch.
>> The low frequency design probably uses a common source design 
>> whilst the VHF version employs a pair of common gate devices.
>> An RF transformer connected between the the common drain and 
>> the positive is used to drive the load.
> OK, so I feed the input (of suitable gain) to a trifilar (or bifilar
> with tap) wound toroid to get the phase and antiphase.
> And the rest is just a pair of standard JFET RF amplifiers.  I.e., I
> should use standard JFET RF amplifier biasing techniques, either employ
> a long tail or, alternatively, measure the pinch-offs and Idss's and
> pick my source resistors appropriately.
> If I'm getting all this right, the circuit looks something like the
> attached.  Yes?
> Thanks for the input.
> -ch
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Biasing is a little more complex than that.

The idea is that each FET is alternately driven into conduction or cutoff.
When conducting the source resistor is selected to ensure that with the 
maximum amplitude signal applied to the gate the drain current doesnt 
exceed the FET Idss.
This ensures that the FET gate is always reverse biased. The series RF 
feedback produced by the source resistor linearises the FET transfer 
function so that when it is driven by a high amplitude sinusoidal gate 
voltage a rectified 1/2 sine wave drain current pulse is produced. The 
series feedback also reduces the flicker phase noise. When the second 
FET drain is connected in parallel with the first it produces a 1/2 
sinewave drain current pulse 180 degrees out of phase with that produced 
by the first FET so that the sum of the drain currents is a full wave 
rectified sine wave. To minimise the fundamental frequency component of 
the total drain current the amplitude of the 2 antiphase 1/2 wave 
rectified sine waves must be equal. The FET matching and bias trimming 
is used to maximise suppression of the fundamental component in the 
total drain current. Like all circuits relying on the switching action 
of an active device, the feedback and bias components must be optimised 
for the particular gate drive levels used. The gate drive voltage 
amplitude range for satisfactory operation will be around 5dBm. 
(~1.8:1). The gate drive amplitude will need to be around 8V pp for most 
silicon JFETS.

Coupling the FET sources together either directly or via a low RF 
impedance capacitor reduces the extent of the transition region where 
both FETS are conducting whilst ensuring that the series feedback 
produced by the source resistor(s) is effective in controlling the total 
drain current noise throughout the cycle.


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