[time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?

Luis Cupido cupido at mail.ua.pt
Tue Dec 11 20:07:19 EST 2007


Hi Bruce and Scott.

 >> What about sampling both the VXCO and 1PPS at a 200MHZ rate?
 >> That should determine the phase difference within no more than a 10ns
 >> inaccuracy.
 >>

Simplicity is good but when using a CPLD or an FPGA no need to get
simple if a better design still fits inside the chip ;-)

Indeed those style of phase measuring schemes have far better 
performance than the simple flip flop or similar.

I say this because I had all the logic on a CPLD to play with
so I tried a large number of phase locking schemes and
could compare them.

First of all the lock capture range can become a bit
independent of the integration time with a proportional phase lag
counting method. Some counting methods will inherently search for lock
when lock is lost. Some of those methods also have lock acquisition 
times orders of magnitude smaller.

On the other hand on CPLD (or FPGA) complexity doesn't cost more as
this stuff is ultra extra small considering the size of
a today's CPLD (eg. maxII w/ 1570 macrocells). No matter what you do
a medium CPLD will be only used 10 to 20% not more.

What I use on the reflock II is a time lag counter from the 1pps to
next clock, and this value drive a dac. Only a small integration time
is done digitally and the large integration time if one requires that
is done with a classical R and C without any active components right
before the Vtune of the VCXO. Therefore not a big DAC resolution is 
required (I use 12-14bit) since the averaging is on the outside in an 
analog filter in which simple 64 seconds integration time will grant
you 6 bit more resolution.

It may look a strange combination of a modern devices and a old 
fashioned filter but it had by far outperformed all the designs I could
test w/ microporcessors + dac (in which some noise did get through),
or lack stability.

Luis Cupido
ct1dmk.
http://w3ref.cfn.ist.utl.pt/cupido/













Bruce Griffiths wrote:
> Scott
> 
> Scott Burris wrote:
>> OK, so for the DAC piece, why not just use an NXP LPC ARM chip for the
>> microcontroller, and use a 32bit PCM output followed by a low pass filter as
>> the VXCO EFC?  The DAC just needs high resolution, not accuracy, right?
>>   
> True, but a Sigma delta DAC has far superior performance to a PWM DAC or
> a standard DAC especially when the long term stability is not critical
> and a faast response isnt required.
> NIST use sigma delta DACs in their precision AC waveform generator and
> to calibrate their Johnson noise thermometer systems.
>> Or would the switching noise from the processor modulate the control
>> voltage?
>>   
> Its best to have the processor drive an external current steering switch
> (74HC4053) to switch a stable current into the summing junction of an
> inverting opamp.
> If you want I can send you a suitable circuit schematic.
> With a suitable circuit one can just use a voltage reference and a
> resistor to set the current, a spare  analog switch can be used in
> series with the feedback resistor to provide temperature compensation 
> (important for good short and medium term stability). HP/Agilent in
> effect use a similar temperature compensated current steering technique
> in their 34401A 6.5 digit DVM.
> Ulrich has uses similar techniques albeit with the sigma delta DAC logic
> implemented in a gate array to achieve high resolution and good short
> term stability.
> In this application the DAC need not respond as fast so it can be
> implemented in software.
>> I would hope the filter would clean any such noise, but I'll be the first to
>> admit
>> that the farther we get into the analog domain, the more I'm out of my
>> comfort zone.
>>
>> I'm still trying to wrap my brain around the phase detection piece of this.
>> I've studied the Shera controller with it's 24Mhz oscillator and divided
>> down
>> sample of the VXCO and I'm can't get past thinking that this ends up
>> adding jitter.  With more modern parts can't the phase be measured more
>> directly?  What about sampling both the VXCO and 1PPS at a 200MHZ rate?
>> That should determine the phase difference within no more than a 10ns
>> inaccuracy.
>>
>>   
> Eliminate such unnecessary cost and complexity with a single D flipflop
> phase detector (D connected to 10MHz signal or a divided down
> subharmonic thereof, CLK connected to PPS) the circuit will
> automatically adapt to achieve a resolution determined by the PPS jitter
> (picoseconds if you have a good enough PPS source, a few nanosec with a
> sawtooth corrected PPS signal from an M12M timing receiver, a few tens
> of nanosec with an uncorrected PPS signal from an M12M timing receiver).
> Thus its resolution is far better than when using a 24MHz clock and its
> also cheaper and the hardware is less complex. Using a 200MHz clock just
> increases the cost and power consumption without significant benefit
> over the simpler D flipflop phase detector.
> However you will need to write suitable software to process the D
> flipflop output samples.
>> Or use a pulse stretching technique to amplify the short time intervals into
>> something
>> more easily measured, although that's beyond what I'm familiar with.
>>
>>   
> Again easily done but more complex than required.
>> I've read the PTTI presentation about using a DS1020 delay line to
>> de-sawtooth the
>> 1PPS signal -- that's a pretty interesting idea.  At least the chip is
>> available in Qty 1,
>> at $30!
>>
>>   
> That is a very good idea for getting the maximum performance with a D
> flipflop phase detector and an M12M or similar GPS timing receiver.
> You can do far better when using GPS carrier phase disciplining
> techniques and the GPS receiver has all the necessary high resolution
> phase measurement circuitry built in.
> However considerable software development is required together with a
> GPS receiver that makes the GPS carrier phase measurement data available.
>> It just seems that the designs I've seen could use a refresh with some more
>> modern
>> circuitry.  At the very least the Shera controller could have much of its
>> logic put into
>> a single CPLD these days.
>>
>> Scott
>> _______________________________________________
>>   
> The Shera controller is a dead end, it doesnt have sufficient resolution
> and whilst increasing its resolution is possible there are simpler,
> better and cheaper ways to achieve this.
> 
> Bruce
> 
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