[time-nuts] Metastability in a 100 MHz TIC

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Thu Jul 19 17:47:12 EDT 2007

Richard H McCorkle wrote:

>    With the discussions here on metastable states in TIC
> counters, I am asking the experts on the list for their
> opinion if the performance of this design would improve
> by adding a shift register synchronizer between the phase
> detector output and the count enable input of the 74F163A
> TIC to reduce metastable states. The 74F series has the
> best reliability figures from metastable effects of all
> the TTL logic families according to the data I have read.
> Each D F/F counter cell in the 74F163A has the clock applied
> directly to the F/F, so no clock gating occurs. Instead the
> input data is gated by count enable signals for each cell and
> either the cell output is sent to the D input if the count
> enable is low, or the previous cell output is gated into the
> D input on carry if the count enable is high with D latched
> into all F/Fs on each clock rising edge. While I see the need
> for a synchronizing shift register in a gated clock design
> like the original Shera controller, is it necessary for best
> performance in a GPSDRO application with a 74F163A 100 MHz TIC?

It is always advisable to use a synchroniser to substantially reduce any 
bias in the averaged phase due to metastability.
However unless there is very high isolation between the 100MHz XO and 
the LPRO output as well as the 100MHz XO the divided down output of the 
LPRO injection locking of the 100MHz oscillator may be a more 
significant source of bias in the averaged phase. If the PPS signal from 
the GPS timing receiver has sufficient random noise (~10ns) then this 
should not be an issue.

When designing a synchroniser it is useful to have a quntitative model 
of the metastability characteristics of the devices used so that a 
reasonably accurate estimate of its output metastability rate can be 


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