[time-nuts] Software Sawtooth correction prerequisites?

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Mon Jul 23 19:32:22 EDT 2007

Tom Van Baak wrote:
>> This sure sounds like a more complicated measurement than is necessary
>> to me. If you have a 10 MHz oscillator, simply feed it into the "D"
>> input into a latch clocked by the de-sawtoothed GPS 1PPS. The output of
>> the latch is a 0 or 1 depending on the precise phase of the oscillator.
>> You want this latched 0/1 measurement to average to ½ over a long term
>> (seconds). As the statistics deviate from a 50/50 split, you tweak the
>> oscillator. The ~1 nsec of residual noise from the sawtooth corrected
>> GPS rcvr acts a natural dither. No counters, no ramps, no big A/D
>> converter -- it couldn't be simpler! And if the 10MHz (=> 100 nsec phase
>> ambiguity) is too fine for your oscillator, then divide it to 5 MHz
>> (=>200 nsec) or 1 MHz (=> 1µsec). This should be good enough to pull in
>> a xtal that is off by 1:10e6.
> This sounds really simple and irresistible. Have you or Rick
> tried it out? I see instead of a TIC (Time Interval Counter)
> you have a TAC (Time Average Controller ;-)
> Not just GPS 1PPS noise but any oscillator noise (jitter), if
> large enough, is also a source of natural dither. Sounds like
> this design would be especially ideal for a low-end GPSDO;
> i.e., one that only needs to be accurate to 10^-9 or 10^-10.
> Did you envision that the OCXO EFC would be driven by a
> statistics-collecting microprocessor and a high-resolution
> DAC? Or is there some clever way to tie statistical results
> of the D-latch to the EFC and avoid the DAC too?
> /tvb 

Perhaps a software implementation of a 1 bit oversampled DAC the 1 bit 
output of which is low pass filtered to control the EFC input is the 
closest approach to this ideal.
With an appropriate algorithm the idle tone and inherent instability 
problems (of high order modulators - 3rd or higher order) of the sigma 
delta modulator will not occur.
An oversampling ratio of 1000 - 10000 should readily be possible 
together with a resolution of 24 bits or more with low gain and offset 
tempcos together with a monotonic transfer function. A low integral non 
linearity isn't necessary as the EFC control input transfer function 
typically isnt that linear. Relaxing the integral linearity spec 
simplifies the design considerably. A 1 bit output also simplifies 
isolation (either optical or chip scale transformer isolation??) of the 
DAC from the processor should this be required.


More information about the time-nuts mailing list