[time-nuts] GPSDO Question

Magnus Danielson magnus at rubidium.dyndns.org
Sun Sep 2 17:08:04 EDT 2007


From: "Tom Van Baak" <tvb at LeapSecond.com>
Subject: Re: [time-nuts] GPSDO Question
Date: Sun, 2 Sep 2007 13:13:39 -0700
Message-ID: <000901c7ed9d$c07d3d30$0300a8c0 at pc52>

> ); SAEximRunCond expanded to false
> Errors-To: time-nuts-bounces+magnus=rubidium.dyndns.org at febo.com RETRY
> 
> > Jerry
> > 
> > It is amusing/distressing to see that the myth that using an FLL to lock
> > an oscillator to the PPS output of a GPS receiver is a good approach
> > still persists.
> > The optimum solution is a phase lock loop.
> > Whilst building an FLL is instructive/educational, if you want the best
> > GPSDO performance you should really use a PLL.
> > 
> > Bruce
> 
> It would seem for timekeeping applications, a PLL-based
> GPSDO will inherit the long-term accuracy of GPS with
> great fidelity.
> 
> But for many frequency (e.g., transmitters) or time interval
> applications (e.g., frequency counters with finite gate times),
> I'd like to understand, in detail, what the difference between
> a PLL- and FLL-based GPSDO really is.
> 
> Can someone point me to real data or even simulations
> with plots that show rms or adev differences between the
> two camps?

I'm sure there is alot of it if you only look carefull enougth. There is alot
in the GPS tracking camp. As always, FLLs are great ways to get started in
tracking in quickly (they certainly beat PLLs) but for stability the FLLs
residue errors, it is basically a derivate measure of the incomming phase and
errors will result in zig-zagging around the goal. This is a D or PD-regulator,
where as a PFD based PLL becomes a PID-regulator. However, onces lock has been
acheived the D-term (frequency) can be removed as the PI-regulator is usually
supperiour unless you expect very big phase-derivations on the input to cause
the the PI-regulator out of lock.

This is the classical books.

In addition, it is worth mentioning that several PFD detectors have problems
with the how internal gate times cause excess push-pull operation in the
charge-pump and results in excess pumping in frequency. Works well for some
applications, but not for others, especially low-jitter high step-up frequency
multiplication.

It is clear that a well done PLL is better and FLL. PLLs is however being
outperformed by Kalman filters. This is all covered in literature, so I don't
think we need to measure things, it is already established.

There are FLLed GPSDOs out there. For many purposes they are sufficienly good,
so it is not necessarilly a *BAD* thing. Good FLLs is limited by PPS resolution
jitter anyway.

Cheers,
Magnus



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