[time-nuts] GPSDO Question

Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Sep 4 21:48:36 EDT 2007


Bert
Bert wrote:
> He everyone,
>
> Just a few points/questions I would like to make regarding the discussion FLL vs PLL vs my design.
>
> One question that I have is regarding FLL vs PLL. The statement that a PLL is better than a FLL on a GPSDO may make sense when looked at from an analog loop and discrete phase comparator signal perspective, but what about the software that closes the loop? For example, the software may provide the ability to not make a frequency adjustment if the frequency difference (or phase difference) is too small. How does this come into play when comparing the two approaches? In other words can we make the software-based FLL a better perfromer so that the claim that PLL is better may not be as obvious?
>
>   
Throwing away information as you suggest almost invariably degrades
system performance.
You could improve your system somewhat by eliminating the 16 second
blanking period whilst you wait for the OCXO to settle.
This delay is unnecessary, a stable loop is possible without it.
The point of the loop is to stabilise the OCXO frequency not to measure
it as accurately as possible.

Using a PWM DAC as you have is almost never a good idea as the PWM
modulation frequency components need to be attenuated by at least 120dB
to avoid significantly degrading the OCXO performance via low level
modulation of the OCXO frequency by the residual PWM signal. Your simple
low pass filter is unlikely to achieve this. Using a conventional DAC
(suitable 16 bit DACs are relatively inexpensive these days) minimises
this problem, however if it is dithered the dither modulation frequency
components need to be attenuated to below the OCXO noise level. If the
dither amplitude is only a few bits (it should almost always be greater
than 1 bit) then filtering the dither components is a somewhat easier
proposition as 60dB attenuation or so should be adequate (with a 16 bit
DAC). However feedthrough from the DAC digital control signals also has
to be attenuated adequately, this is a more difficult but potentially
solvable problem.

Did you actually use a ground plane on your PCB?

Removing the frequency dividers from the board should also improve
performance as they are yet another source of unwanted modulation
frequencies for the OCXO EFC input.
Ideally you should use a distribution amplifier to feed various systems
such as the FLL system and any such dividers a well shielded enclosure.

> Finally, just a reminder: I make no claim of mind-blowing
> performance with my design. From the beginning, it has been clearly stated
> that the expected short term accuracy of the VE2ZAZ design (assuming a
> decent OCXO is used) should be better than 1x10^-9. My website also
> provides the same information. The feedback that I have received from
> the users correlate with this. I like to see my work as allowing the 100+ users to learn more about disciplining an oscillator and obtain a better 10MHz reference. Nothing more than this.
>
>   
Your performance measures are less than satisfactory for an informed
decision of whether the performance is adequate for a particular purpose.
Plots of the Allan deviation versus tau are desirable as well as some
idea of the level of any incidental sidebands.

Achieving an accuracy of 1E-9 with a 10811 or similar OCXO is about
10-100 times worse than can be achieved with a relatively inexpensive
PLL disciplining technique.
Surely if an accuracy stability of 1E-9 is adequate a lower performance
(and cheaper) oscillator would suffice.

> Bert, VE2ZAZ
> http://ve2zaz.net
>   
Bruce



More information about the time-nuts mailing list