[time-nuts] V standards

[Bruce Griffiths]

SAIDJACK at aol.com wrote:
> Hi Bruce,
>  
> yup, I thought that circuit and it's claim to 32 bit resolution was over  the 
> top too, I didn't actually read the details.
>  
> Coarsedac changes are an issue as you mentioned, but one can get around  them 
> by scaling the two dacs in a way to only use a couple of bits from the  
> coarsedac, and operate most of the time using just the fine dac.
>
>   
In principle embedded calibration of the errors at coarse DAC
transitions should be possible.
> This is similar to a mechanical coarse adjustment (such as on the  10811A) 
> setting the approximate voltage range, with the EFC done by  the fine dac.
>  
> If you use a 16 - 18 bit fine dac, and 6 - 8 bits of a coarse dac then  this 
> works quite well, and with a low aging SC-cut crystal you may never see a  
> coarsedac change, while still having over 21+ bits of overall resolution.
>  
> It's fairly straight forward to improve the resolution of a good Dac by 2,  3 
> or even 4 bits using PWM, see Tom's description of how this is done in a  
> Z3801A on leapsecond.com.
>   
Yes this can be made to work well, as can using sigma delta modulation
however one then needs a good random number generator for dithering the
loop quantiser to eliminate idle tones which are otherwise somewhat
problematic. The effect is very easy to simulate using Matlab or even by
writing some simple code.
Using a synchronous filtering technique simplifies the filtering
considerably. The usual sigma delta modulation techniques advocated to
increase DAC resolution don't work that well due to the idle tones they
generate.
>  
> So in short, one could use two identical 16 bit dacs, scale the resistors  so 
> that only the upper 6 - 7 bits are used as a coarsedac, and use the fine dac  
> as a 20 bit dac with PWM resolution-enhancement (16 to 20 bits). This would  
> yield more than 26 bits theoretically from 2 inexpensive 16 bit dacs, and the  
> noise could be removed by low pass filtering using an analog filter with  say 
> less than 0.3Hz cutoff frequency similar to the Z3801A circuitry. In this  
> case the coarsedac can probably even be exchanged for a simple high-stability  
> pot.
>  
>   
Synchronous filtering of the DAC output would result in much faster
settling times with low modulation artifacts.
> It does require a bit of real time firmware to do the PWM enhancement of  
> course.
>  
> bye,
> Said
>  
>  
>   
The technique advocated in the article may have fewer artifacts due to
DAC settling time issues.
Its also a lot cheaper since very tight tolerance stable components
aren't required.
The output should also be somewhat quieter.

Bruce