[time-nuts] V standards

[Richard Moore]

On Dec 2, 2008, at 12:25 AM, Bruce and PHK wrote:

>> <clip>
>> There was a recent Design Idea in EDN or Electronic Design (don't  
>> remember
>> which one) where someone claimed 32 bit resolution out of two 16  
>> bit dacs. That
>>  claim is ridiculous of course due to noise and matching etc, but  
>> you can
>> probably get 20 - 24 bits resolution and accuracy out of a  
>> cascaded system with
>> some care.
>>
>> bye,
>> Said
>>
> If you build this circuit using the values shown in the schematic you
> won't actually achieve 20 bits performance.
> One of the resistor values is incorrect.
> The resistor matching requirements aren't anywhere near as  
> stringent as
> one may think on first glance.
> With some subtle alterations to the operating mode the resistor ratio
> matching tolerances can be relaxed considerably.
> In closed loop digital control systems the circuit noise should be at
> least 1LSB or so to maximise performance.
> The trick is to increase the DAC resolution until this condition is
> achieved and not increase the noise to meet the condition.
> 20 bit resolution performance is easy to achieve, 24 bit performance
> requires 2 a little more work.
>
> Actually monotonicity to about 26 bits was claimed with noise a bit
> below 1ppm.
> However since the noise varies with the DAC output such claims are
> perhaps a little too simplistic.
> The noise can be reduced when required by using a better reference.
> Any drift in DAC gain and offset could be compensated by a Kalman  
> filter
> should they become significant.
>
> The major advantage of such a DAC is the inherent monotonicity which
> cannot be achieved and maintained (around coarse DAC transitions)
> without frequent calibration when the outputs of 2 16 bit DACs are  
> combined.
>
> Bruce

Bruce, is there a way for non-subscribers to see this article?

Dick Moore

> ------------------------------
>
> Message: 8
> Date: Tue, 02 Dec 2008 08:25:00 +0000
> From: "Poul-Henning Kamp" <phk at phk.freebsd.dk>
> Subject: Re: [time-nuts] V standards
>
>> Coarsedac changes are an issue as you mentioned, but one can get  
>> around  them
>> by scaling the two dacs in a way to only use a couple of bits from  
>> the
>> coarsedac, and operate most of the time using just the fine dac.
>
> If you are controlling this with a microcontroller, there is an  
> alternative
> you should consider:
>
> Use only a single DAC and then PWM modulate its output, followed
> by a low-pass filter.
>
> -- 
> Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
> phk at FreeBSD.ORG         | TCP/IP since RFC 956
> FreeBSD committer       | BSD since 4.3-tahoe
> Never attribute to malice what can adequately be explained by  
> incompetence.
>

Poul, how do I PWM a DAC that is itself a PWM device? This question  
is prompted by the DAC I'm using in Bert Zauhar's FLL GPSDO, which is  
a dithered 10-bit DAC in a PIC chip that results in 14-bit  
resolution. I'd like to have a simple way to get 2 to 4 extra bits of  
resolution out of this. Can you recommend some design resources to do  
this?

Dick Moore