[time-nuts] Sub Pico Second Phase logger

[Bruce Griffiths]

WarrenS wrote:
> Building a Sub Pico Second phase detector.
>
> I was inspired to build this project yesterday after downloading and trying   
> Ulrich Bangert's 'DF6JB's Plotter 2008-10-10' program with its unbelievable 
>  flexible user Interface capabilities.  http://www.ulrich-bangert.de/html/downloads.html
> What I needed was a Phase detector to use with the 'Plotter' program.
> I decided to see what it takes to build a simple high resolution, sub Pico second, 
> linear phase logging detector using standard off the self IC's.
>  
> How If works:
> The 5 or 10 MHz signal to be measured is buffered and toggles a 
> synchronous divide by two or four FF. This gives a 2.5MHz square wave and its complement. 
> Each side of the flip-flop connects to two of four XOR gates.
>
> The 10 MHz reference signal goes thru a matching buffer and then to a pair of synchronous 
> Flip-Flops that provide a zero and a 90 deg phase shifted 2.5MHz square wave.
> Each of these goes to two inputs of the XOR gates. The four XOR phase detectors 
> are connected to give four PWM type XOR phase detectors, each separate by 90 deg.
>
> Each of the four XOR outputs are buffered by a cmos buffer gate 
> that has been powered by it's own 5 volt reference supply.
> The buffer outputs then goes thru a multi-stage passive RC filter set up to 
> give two differential filtered PASSIVE + - 5 volt outputs, 90 deg apart.
>
> Logging  Data:
> For the most flexible and best  performance, two differential 16 plus bit ADC's 
> should be used, each connected to one of the dual differential Phase detectors.
> After using the appropriate Analog RC filters, oversampling, digital filters, and digital 
> scaling, you get a file with a single column of data to feed "Plotter" the phase 
> difference of the two 10 MHz signals. 
>
> The Data scaling and processing:
> For simple controlled short term or lower resolution data taking a PC Multimeter, 
> if it is isolated so that you can use it differentially will work.  If not you need to add a differential amp. 
> For best performance, process the phase data from the two differential phase detectors 
> through two identical digital filter algorithms.
> Doing this real time on a PC or after all the data is recorder on a XL spread sheet both work for me.
> Besides the filtering, the spread sheet or PC needs to also do the linearizing by 
> ( K1* Phase1_Data) + (K2 * Phase2_Data).   
> K1 and K2 are the sine value of their respective Phase detectors.
>
> One of the several tricks to why this can provide orders of magnitude better 
> performance than is generally obtained from similar type phase detectors 
> is because of the four matched Phase detectors that are added, subtracted 
> and combined and linerized in such a way as to cancel the type of errors 
> found in single XOR phase detectors.
>
> Preliminary Performance
> The noise floor that I have seen while feeding the same low noise osc, to both inputs, 
> is around 10 uv peak to peak at low Bandwidths, at zero phase,  using a 6 digit DVM 
> with a slow filter which corresponds to <<1 ps. Test are still underway to see what the 
> lower limit is, and what the sensitivity to the environment is.
>
> This is just the start of an on going learning project, It is just at the breadboard stage and 
> needs to be verified, critiqued, cleaned up and packaged up. 
> Noted that when working with sub ps resolution, extra care needs to be taken.
> Although it looks to be a standard digital circuit, It is not. It is a very sensitive Analog circuit 
> capable of giving 1 part in a million type of resolution. It can resolve path distance changes 
> in the 1/100 to 1/1000 of an inch, and needs to be built with care and 'respect'.   
>
> Another use (beside watching just how noisy your "GOOD " osc is),
> It can be used to compare and adjust the freq differences between two osc 
> very quickly and with more resolution than most can use.
> 1 E-12 freq difference gave several counts per second change on 
> the DVM, and with the DVM updating at several times a second, 
> it made fine freq adjustments much easer than slower monitoring ways.
>
>
> If you know of other simple high resolution phase detectors, 
> or see any problems or improvements 
> with the idea, I'd like to hear from you.
>
> Have fun
> WarrenS
>   
Warren

Since HCMOS buffers typically have about 4ps of random propagation delay
jitter and ACMOS devices typically have about 1ps of RJ this isnt too
surprising.
Newer logic families may have even lower random jitter.

Doesn't this phase detector, like all digital phase detectors, have
significant non linearity at the ends of its range?
In the case of an XOR gate phase detector this is caused by the finite
slew rate of the gate output.

With the quadrature phased outputs at least 2 of the phase detectors
will be operating in the linear part of their range.
The particular pair that are linear depends on the relative phase of the
2 inputs.

One or more of the ubiquitous 24 bit resolution sigma delta ADCs with
differential inputs and a reference derived from the XOR power supply,
will for CMOS XOR gates probably be a relatively inexpensive replacement
for the DVM int he final system.

If one used an FPGA or CPLD for this as the internal crosstalk may limit
performance to a few tens of picosec noise for 1 sec averaging unless
differential I/O logic such as LDVS, ECL etc are used.
Although the circuit is simple enough not to warrant an FPGA it would be
useful to have programmable dividers for each input to allow comparison
of input frequencies that arent either nominally equal or have a
frequency ratio of 2:1. Using external retiming flipflops should cure
the crosstalk problem with such a divider.
In practice such a divider should perhaps be an external device with its
own power supply and enclosure.

Such a divider can be used to increase the effective range of the phase
detector at the expense of its resolution.

Bruce