[time-nuts] Sub Pico Second Phase logger

Joe Gwinn joegwinn at comcast.net
Mon Dec 22 22:07:30 UTC 2008


Bruce,

At 9:08 PM +0000 12/22/08, time-nuts-request at febo.com wrote:
>
>Date: Tue, 23 Dec 2008 10:08:35 +1300
>From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
>Subject: Re: [time-nuts] Sub Pico Second Phase logger
>To: Discussion of precise time and frequency measurement
>	<time-nuts at febo.com>
>
>Joe
>Joe Gwinn wrote:
>>  At 2:01 AM +0000 12/22/08, time-nuts-request at febo.com wrote:
>>  
>>>  Message: 4
>>>  Date: Mon, 22 Dec 2008 11:19:06 +1300
>>>  From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
>>>  Subject: Re: [time-nuts] Sub Pico Second Phase logger
>>>  To: Discussion of precise time and frequency measurement
>>>	<time-nuts at febo.com>
>>>
>>>  Joe
>>>
>>>  Joe Gwinn wrote:
>>>   > Bruce,
>>>    
>>>   >>
>>>
>  >> [snip]
>
>  >
>  >>>>  [BG]  The DDS based equivalent (of the dual PLL Diophantine 
>synthesiser) would
>>>>>   use a pair of DDS chips each replacing a conventional PLL in the
>>>>>   Diophantine frequency synthesiser, the output frequency of each having
>  >>>>  zero phase truncation spurs.
>>>>>
>>>>>   Both DDS clock sources should be spur free and have a frequency ratio
>>>>>   that is a selected fixed rational fraction.
>>>>>   
>>>>>        
>>>>   [JG]  A M/N PLL chip can arrange this.  I recall that Silicon Labs makes
>  >>>  such a chip, which requires a parameter load on power-up, so a
>  >>> computer or FPGA is needed.
>  >>    
>>
>  > 
><https://www.silabs.com/products/clocksoscillators/clocks/Pages/default.aspx>
>>
>>  Also of interest:
>>
>> 
>><https://www.silabs.com/products/clocksoscillators/clocks/Pages/Any-RateJitterAttenuatingClockMultipliers.aspx>
>>
>>
>>  
>The close in phase noise of these devices appears to be very high.
>This may preclude their use in a system that just uses 2 of them directly.

The SiLabs "Precision" units claim very low jitter (and thus low 
phase noise).  The above "jitter-attenuating" units are in this 
group.  I see that the spec numbers are still TBD though.

There may be other makers; this is a very competitive area.  I got 
the source from a RF engineer at work.

By the way, when we first used one of the simple PLL chips, we had 
failures.  It turned out that one had to bake the chips (to drive 
moisture off) longer than the original instructions said, and some of 
the chips cracked during soldering.  The new instructions eliminated 
the problem.

I suppose that all single-IC solutions will have worse phase noise 
than a well-engineered discrete unit, simply because it's hard to 
prevent undesired leakage of signals between parts of the the IC. 
However, the ICs may still be more than adequate, and are a whole lot 
easier than rolling our own discrete units.


>However in the high resolution version where the output frequencies of
>the 2 M/N synthesisers are each divided by a large factor before being
>added and subtracted from the reference (10MHz ??) frequency the
>resultant close in phase noise will be much lower.

And can be combined with use of the precision units.


>Control of the close in spur levels produced by the NCO may also be an
>issue.

If the division ratio is an integer, the spurs are reduced.

Analog Devices has a web calculator that's useful for fast 
exploration.  The calculator operation is explained and the reference 
provided in their big tutorial on DDS principles.


>  >> M and N only have to be relatively prime (ie the GCD of M and N is 1).
>>>  The ratio of M/N should also be close to 1.
>>>  If the spacing of the phase truncation spur free output frequencies is
>>>  about 10kHz (for either DDS) and M, N ~ 1000 the resultant mixer output
>>>  frequencies would have a spacing of about 10Hz which may be adequate for
>>>  this application.
>>>    
>>
>>  I found and read the basic articles, which can be downloaded from
>  > Prof Sotiriadis' website:
>>
>>  <http://www.ece.jhu.edu/~pps/WEB/Publications/pub.html>
>>
>>
>There is also US patent 5267182.

I did find 5,267,182 while searching for Sotiriadis' patent, but 
forgot to mention it.  Don't know what the difference is.  In the US, 
patent applications are made public after 18 months, or immediately 
if the person is also applying for a European patent.  The US Patent 
Office is years behind, so patent issuance may be a while.


>  > Items J10, J13, and J15 seem particularly relevant.
>  >
>>  All one needs is the M/N chip, although one can certainly use DDS chips.
>>
>>
>>
>Using a DDS avoids the requirement for a pair of low phase noise VCOs.

If we can control the spurs, many DDS chips are very good.


>  >>  >> A conventional mixer would then be used to either add or subtract the
>>>    
>>>>>   two DDS output frequencies.
>>>>>   If the ratio of the 2 DDS clock source frequencies is appropriately
>>>>>   chosen the spacing between the resultant mixer output frequencies can be
>>>>>   much finer than the spacing between the truncation spur free outputs of
>>>>>   either DDS chip.
>>>>>   The DDS and mixer outputs should be filtered to remove harmonics and
>>>>>   other unwanted frequencies.
>>>>>   
>>>>>        
>>>>   If the DDS chips are well chosen, we will get sin and cos outputs,
>>>>   and so can implement a dual-mixer phasing scheme to yield only the
>>>>   sum frequency or only the difference frequency, greatly reducing the
>>>>   amount of filtering needed.  The better balanced the channels are the
>>>>      
>>>   > better the cancellation of the unwanted term.  This is basically the
>>>   > phasing method of single-sideband signal generation.
>>>    
>>
>>  This would be a reason to use DDS chips instead of M/N PLL chips,
>>  unless there are M/N PLL chips that provide quadrature outputs.
>>  SiLabs Si5338 may suffice, as it allows one to control the relative
>>  phase of its outputs.
>>
>>
>>  
>If one were to divide the output frequency of the diophantine
>synthesizer by 4 using a 2 bit Johnson counter then quadrature phase
>outputs are available.
>However the filters used to extract the fundamental from the divider
>outputs would need to be matched.
>If the diophantine frequency synthesiser output frequency doesn't vary
>too much one can always use a quadrature hybrid.

This seems like a lot of work.  Hmm.  Now that I think of it, the 
SiLabs chips emit square waves (logic signals), not sine waves.  Back 
to DDS chips, it seems.

Joe



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