[time-nuts] New topics (was Re: He is a Time-Nut Troublemaker....)

Hal Murray hmurray at megapathdsl.net
Tue Dec 23 21:13:29 UTC 2008


>> PLL up by a factor of N, use that to drive a DDS, then filter.  Maybe
>> a pair of DDSes will get better tracking.

>> For each possible phase offset, you need N slots in the table.  (N/4
>> with more work)

> If doing phase noise or short term stability measurements, wouldn't
> the noise of the DDS impact the results?

I'm not a wizard on this stuff.  I think there are 2 sources of errors in 
traditional DDSes.  One is round off errors in the sin/cos tables (and D/A).  
The other is spurs because the step size on the index into the table isn't 
constant.  (It's mostly X, but occasionally X+1 or X-1)

I think the spurs depend upon N and who designs the table.

If you use an all-in-one DDS chip, you get their choices.  I think it will 
work cleanly if N is a power of 2 so there are no low bits in the accumulator.

If you design your own, you can use a not-quite traditional DDS.  Say N is 5 
so you have 5 steps per cycle.  Just count up from 0 and reset when you get 
to 4.  That's 3 bits.  Suppose you want 0-360 phase offset by 1 degree steps. 
 That's 9 bits.  So you need a ROM with 12 bits of addressing, 4K.

I think the round off errors will not be a serious problem.  You are making a 
signal with a clean period, no spurs.  You won't make a perfect sine wave, 
but you can filter out the harmonics.

Did I get that right?


-- 
These are my opinions, not necessarily my employer's.  I hate spam.






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