[time-nuts] phase noise questions

John Miles jmiles at pop.net
Tue Jan 22 19:35:23 EST 2008


Doubling your clock frequency adds 6 dBc/Hz to whatever the noise level was
at the input, at all offsets within the doubler's bandwidth.  Only if the
input noise level is near or below the multiplier's own residual noise floor
will the increase be worse than 6 dBc/Hz.

That will not happen when ordinary crystal oscillators and conventional
Schottky-diode multipliers are used together; high-performance active
multipliers are needed only when working with exceptionally clean inputs.
At input noise levels higher than -155 to -160 dBc/Hz, ordinary diode
multipliers will not usually contribute any additional noise.

-- john, KE5FX


> Hello,
>
> I followed with some interest a discussion about a NIST doubler circuit
> using matched FET's and I was wondering if you could get similar results
> using an analog multiplier chip from Analog Devices. It would seem that
> they take some care about device matching and have parts that work up
> to pretty high frequencies. Of course there would need to be some
> filtering
> employed. Oh, and I think those parts do pretty well with temperature.
>
> Also, when using a doubler that is rated in dBc how do you apply that
> number to get an expectation from a given starting dBc oscillator. So
> if my 10 MHz clock is -125dBc and I use the NIST circuit, what would
> I see at 20 MHz in dBc?
>
> thanks in advance,
> steve
>
>




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