[time-nuts] Low phase noise digital divider (in 600MHz to10MHz area)

[Anders Time]

Have been locking around for a good article on how to design a good Low
phase noise digital divider(in 600MHz to 10MHz area), but the have not found
any good literature. Today most people talk about regenerative dividers, but
are a rather complex subject.
Does anyone have experience in what logic family that have the lowest noise
TTL, AC, HC, F etc?
What is the upper limit for ECL diviers? My first idea was to use ECL to
divide down to 100MHz area and then to use lower noise TTL to go down to
10MHz.
What about edge-conditioning circuit at divider input? Have seen people talk
about it, but no info what it does?
Thanks
Anders