[time-nuts] Frequency divider design critique request

[Bruce Griffiths]

Hej Magnus
Magnus Danielson wrote:
> David,
>
>   
>> As I've mentioned before, I've been working on the design of a frequency
>> divider to go with my TB.
>>
>> The idea is 10MHz sine in from TB, output 2.5Vp-p 50% duty cycle square wave
>> into 50R (5V into 1M), at 10Mhz, 5MHz, 1MHz and decade selectable 100kHz
>> down to 1Hz.  All rising edges synchronised to the 10MHz clock rising edge
>> (or as near as I can get with 74AC logic).
>>     
>
> Good initial concept.
>
>   
>> With a considerable amount of constructive criticism from Bruce Griffiths
>> (thank you again Bruce) I believe the design now to be complete.   
>>
>> The aim is to have as low a level of nasties as possible (i.e. fit for
>> time-nuts).
>>
>> All faults are my own - no blame attaches to Bruce!
>>     
>
> The one thing I would do is to hook caps over at R24 to R26, say 10 nF, to
> make the thumb wheel leads less susceptible to noise and less of areal for
> the edges from the CMOS. The thumb-wheel either keep them floating in one
> end or didged hard to +5V. To avoid both E and H fields, a series-resistor
> should be included.
>
>   
You mean?:

1) Connect a 10nF capacitor from each multiplexer digital control input 
to ground.

2) Connect a series resistor (10k?) from multiplexer control input to 
the thumbwheel connector pin.
 
3) Connect a pullup/pulldown resistor from the thumbwheel connector pin 
to GND or VCC as required.
>> I've not yet subjected this design to the ultimate simulation tool (PCB,
>> parts and solder) yet, and I have no means to test it for levels of jitter
>> (phase noise) or similar nasties.
>>     
>
> I am sure we can come up with some arrangement for that. Several handy
> time-nuts around.
>
>   
>> I think that it's now the right time to open the design up for critique from
>> a wider audience before I commit it to copper.
>>
>> I'm therefore attaching the design as a PDF file for your comments.
>>
>> A few comments are in order:
>>
>> 1) The 5Mhz and 1MHz outputs are re-clocked TWICE deliberately to delay them
>> by one clock cycle so they line up with the 1MHz and lower outputs.
>>     
>
> Neat.
>
>   
>> 2) The selected output (at the '4051 mux) from the ripple counter chain is
>> re-clocked to 1MHz before re-clocking to 10MHz as the worst-case delay in
>> the chain of '4017s is large enough that the lower frquencies wouldn't
>> reliably re-clock directly to 10MHz.  
>>     
>
> Good thinking!
>
>   
>> I have also done a PCB layout (4-layer) and I'm happy to send a print of the
>> top/bottom layers to anyone who feels that they want to comment on that
>> (inner layers are ground and power).
>>     
>
> ... and you say they are not of interest?
>
>   
>> Let the brick-bats be thrown!
>>     
>
> I have a lots of bricks around me (my summerhouse is build with old handmade
> bricks) but I wont toss them.
>
> So far, only the thumbwheel is the only minor flaw that I could come up with.
>
> I need to check some more...
>
> I rather have a few questions on why you did not include certain features...
>
> In my experience, having a few extra 10 MHz signals to feed Ext Ref on
> instruments is a good thing. That way you can keep these others at hand for
> various setups you need to do.
>
> I would consider a dedicated 1 PPS output.
>
> I would consider a synchronise feature with a PPS/synchronise input. It should
> be wise to not directly wire it to the counter resets, but provide an arm
> button and maybe a very simple arrangement to indicate "left", "on mark" and
> "right" with red, gren, red LEDs. Just a tought. The arm button could also
> have an electrical input, but I am running into creaping featurism here.
> I think however that synchronisation might be a good thing. That way you can
> shift the phase of the signal to fit your need. Pulling and inserting the
> 10 MHz cable is a very crude way of doing it.
> Maybe it would be just too much fuzz for too little gain, what do I know, but
> I know I would enjoy seeing it.
> A pulse-add/pulse-swallow technique (with a shift in initial divide by 10)
> could be used to provide inc/dec functionality for a manual movement of phase.
>
>   
The only minor problem is that shifting phase by 1sec or so at the 1pps 
output will take quite a while if one were to delete 1 pulse per second 
(to maintain 100ns resolution via pushbutton).
A variable phase adjustment rate would work but that adds considerable 
complication.
One method is to allow phase shifting decade by decade.

Another way to handle large phase adjustments is to use 2 divider 
chains, the master is clocked continuously without phase adjustments.
The slave is adjusted by preloading it with the desired phase shift when 
the master divider rolls over.
This is easiest to do with synchronous decade counters like the 
74XX160/2, however these seem to be hard to find.
However this adds considerable complexity and would be much easier to 
implement in a CPLD or FPGA.
External resynchronising/reclocking flipflops would be required to 
minimise phase modulation of higher frequency outputs by lower frequency 
outputs.
> Cheers,
> Magnus
>   
Bruce