[time-nuts] Frequency divider design critique request

time at johnea.net time at johnea.net
Thu Jul 10 19:15:18 EDT 2008



Hi David,

It looks like your design is pretty far along, so maybe it's too late for this suggestion, but one thing you might consider is replacing the 7400 series logic with a 5V CPLD programmable logic device.

This could offer several advantages:

1) any issues (such as jitter) could be addressed by reflashing the CPLD and may let you avoid hardware PCB changes.

2) new features or applications (specially created triggers or unusual pulse outputs) that may come up in the future could possibly be added, again without PCB changes.

3) a full simulation of the design could performed prior to construction

Xilinx offers a free (as in free beer, not as in free speech) complete programmable logic design simulation and synthesis tool for download from their website. It's called ISE WebPACK. There's a version for windows or linux host:

http://www.xilinx.com/ise/logic_design_prod/webpack.htm

This tool is quite an amazing free download. I had to go through a few gyrations to get the USB "cable", as they call the downloader, to build for linux:

http://wiki.archlinux.org/index.php/Xilinx_ISE_WebPACK_10.1_wUSB_cable_on_ArchLinux-2.6.24

But I'm sure it's easier on windows.

The CPLD's (unlike the FPGAs) are single chip solutions. The XC9500 family is 5V logic compatible and could fit into something as small as a 44 pin package.

The ISE design tool offers built in Verilog, VHDL or CUPL programming laguages, or (and this really amazed me) a built in schematic editor tool! This lets you capture the design, just as you have, in a schematic, and then synthesize the logic and perform a complete simulation of your captured schematic.

You could even just download the tool, capture your existing schematic (there are logic elements for 7400 series logic devices) and use the tool as a simulation engine to test your design. Even if you ultimately plan to use the 7400 parts.

No, I don't work for Xilinx 8-) but I did just finish a design using this tool and was suitably impressed. While I write quite a bit of code in my day to day work, I hadn't designed programmable logic since the old PAL days (way back in the early 80's 8-) I used the schematic capture feature of ISE to input the design and then found my way into writing the control state machines in verilog. Then simulated the functionality and when we built the hardware the whole thing just worked, right out of the box!

(The design ran an A/D converter, captured the results into a static ram, and then allowed SPI access to the ram from an AVR microcontroller)

I know going to programmable logic can seem like a big unknown, but perhaps it's worth just downloading the tool and checking it out.

The CPLD wouldn't replace any of your signal conditioning, fusing, etc, but it could replace the core counters, muxes, etc and give you something that could continue to grow as the years go by.

Very Cool Project!

johnea


On Thu, Jul 10, 2008 at 09:30:56PM +0100, David C. Partridge wrote:
> As I've mentioned before, I've been working on the design of a frequency
> divider to go with my TB.
> 
> The idea is 10MHz sine in from TB, output 2.5Vp-p 50% duty cycle square wave
> into 50R (5V into 1M), at 10Mhz, 5MHz, 1MHz and decade selectable 100kHz
> down to 1Hz.  All rising edges synchronised to the 10MHz clock rising edge
> (or as near as I can get with 74AC logic).   With a considerable amount of
> constructive criticism from Bruce Griffiths (thank you again Bruce) I
> believe the design now to be complete.   
> 
> The aim is to have as low a level of nasties as possible (i.e. fit for
> time-nuts).
> 
> All faults are my own - no blame attaches to Bruce!
> 
> I've not yet subjected this design to the ultimate simulation tool (PCB,
> parts and solder) yet, and I have no means to test it for levels of jitter
> (phase noise) or similar nasties.
> 
> I think that it's now the right time to open the design up for critique from
> a wider audience before I commit it to copper.
> 
> I'm therefore attaching the design as a PDF file for your comments.
> 
> A few comments are in order:
> 
> 1) The 5Mhz and 1MHz outputs are re-clocked TWICE deliberately to delay them
> by one clock cycle so they line up with the 1MHz and lower outputs.
> 
> 2) The selected output (at the '4051 mux) from the ripple counter chain is
> re-clocked to 1MHz before re-clocking to 10MHz as the worst-case delay in
> the chain of '4017s is large enough that the lower frquencies wouldn't
> reliably re-clock directly to 10MHz.  
> 
> I have also done a PCB layout (4-layer) and I'm happy to send a print of the
> top/bottom layers to anyone who feels that they want to comment on that
> (inner layers are ground and power).
> 
> Let the brick-bats be thrown!
> 
> Cheers
> Dave
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