[time-nuts] Frequency divider design critique request

[Magnus Danielson]

From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
Subject: Re: [time-nuts] Frequency divider design critique request
Date: Sat, 12 Jul 2008 12:11:03 +1200
Message-ID: <4877F697.2040700 at xtra.co.nz>

> Magnus Danielson wrote:
> > Why not? It basically solves a problem most of us has, and only a few tweaks
> > away and it solves it fairly generically. The only think it doesn't do well is
> > handling 5 MHz souces rather than 10 MHz. Having that would solve many
> > problems. While not achieving full metrological levels of stability, I am sure
> > it could be handy for several time-nuts never the less. Only a few need that
> > upper level anyway. A good prooven design for enought stability and decent
> > money might be right. I would certainly not mind having a pair of those lying
> > around and I am sure I could put a few into continous use. Now that is my lab
> > alone...
> >
> >
> >   
> Magnus
> 
> A minimalist approach for the 5MHz to 10MHz doubler could use a full 
> wave (diode, BJT or JFET) doubler followed by a series tuned 5MHz shunt 
> trap to minimise the 5MHz content in the output.

Actually, it depends on weither you would like to get a 10 MHz or not.
Another solution would be to run the first divider to /5 rather than /10
and only use the doubler for the 10 MHz output. Ah well.

> If the doubler components were perfectly matched (unlikely) the 
> fundamental trap could be omitted.

Agreed. If the zero of the shunt trap is made low-Q the tuning of the shunt
becomes almost unnecessary. Also, temperature shifts on components would not
shift phase as much.

> The other harmonics are of little concern as the comparator output is a 
> square wave and the rectified sinewave waveform would produce a duty 
> cycle of around 44% at the comparator output.

Unless the duty cycle is important, the overtones help to keep the slew rate
high and this avoids adding too much jitter.

> The diode turn on threshold will alter the duty cycle somewhat but it 
> should still be acceptable at least for clocking the flipflops and dividers.

Agreed.

> If desired a threshold feedback loop could be used to stabilise the 
> comparator duty cycle at 50%.

Good thought. Should be a trivial thing.

> However such a duty cycle stabiliser only works when the input signal 
> waveform is sinusoidal, rectified sinewave or any other signal with a 
> slow enough slew rate.

Indeed.

I was only thinking that maybe there ought to be a buffer from the input
to the rectifier, or else higher frequency energy will escape out towards the
source. At least some isolation should be there.

Cheers,
Magnus