[time-nuts] quick and very dirty phase comparator
bruce.griffiths at xtra.co.nz
Sun Jun 1 19:25:39 EDT 2008
Kasper Pedersen wrote:
> This is to poke my head in, and to share a simple multichannel
> phase comparator/monitor that turned out to be useful.
> I have a few homebuilt boxes that will do ~100ps timestamps,
> I have other uses for them, and tying them up with a single
> long term experiment is unacceptable. So I needed a phase
> comparator that I could rebuild in an hour if I wanted to,
> something in the spirit of TVB's PIC16 divider.
> Something simple.
> The idea is this:
> Beat a number of 10MHz inputs against another clock frequency
> using the input flipflops in a microcontroller as samplers,
> sample a number of times to cover the phase circle, and
> calculate the phase. Beating against 11.0592MHz gives a period
> of 3456 clocks, sampling every 8 clocks gives 432 samples, that
> should give 230ps resolution. Add clock jitter and aperture
> jitter, and precision should be around 500ps.
> How much performance can one get for $10?
> schematic: http://n1.taur.dk/timenuts/phasecomp8.pdf
> samples: http://n1.taur.dk/timenuts/phasesamples.png
> When comparing a 10MHz source with itself through
> a cable delay, the peak noise is 400ps. That's for a
> 300-microsecond acquisition time, which means the
> update rate is limited by how fast I can compute the
> vector and shovel data over to a PC. When monitoring
> beating 10MHz sources with an adjusted (-3ppm)
> microcontroller clock, it's about 600ps peak.
> When misadjusted to be -30 ppm off, it's 1.1ns peak.
> At the moment there is only a crude windows program for
> turning the output into decimal plottable data, so some
> programming skill or beer drinking friend with programming
> skill is required, as well as knowledge of what one wants to
> measure (that's usually the hard part).
> source, hex: http://n1.taur.dk/timenuts/phasecomp.zip
> converter: http://n1.taur.dk/timenuts/phasehex2dec_win.zip
> I'm aware that 600ps is a very large figure in a lot of
> cases but for my oscillators it's good enough.
> /Kasper Pedersen.
Nice, but it would be good to expend a little more money and retain the
26ps resolution that should be achievable with this technique.
One approach is to use an FPGA and examine every cycle, however unless
an FPGA with differential I/O is used the resolution may be limited to
around 50ps or so due to internal noise and crosstalk.
Another approach is to use an external D flipflop clocked at 11.0592MHz
with the 10MHz input connected to the D input and connect the D flipflop
output to an 8 bit serial input shift register clocked at 11.0592 MHz.
The 8 bit shift register output would then be read every 8 cycles of the
Using an external flipflop dedicated to this function should reduce the
noise significantly, provided that a suitable low noise PCB layout (4
layer with GND and power planes??) is used.
Of course with a DSP or other processor having a synchronous serial
input port (most DSPs have 2 or more synchronous serial ports) the
external shift register can be eliminated, however an additional
external flipflop acting as a 1 bit shift register may be useful in
reducing the frequency of metastable states being unresolved when the
data is sampled by the synchronous serial port. Typically the
synchronous serial port may have either a 16 or a 32 bit receive
register. Thus the data word only has to be sampled every 16 or 32
cycles. The thermometer code in the register then has to be decoded to
deduce the time stamp at which the 0 to 1 transition occurred.
When used to compare the phases of 2 or more channels the accuracy of
the 11.0592MHz crystal is less critical.
Even so, it would be better to be able phase lock it to a low noise high
stability reference source.
It would also be possible to use ECL/PECL external flipflops with
differential data and clock inputs for maximum performance.
Then an ECL/PECL to TTL/CMOS level translator is required between the
ECL/PECL fliflop output and the input to the synchronous serial port.
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