[time-nuts] Home built cesium clocks???
stijena at tapko.de
Sun Jun 29 15:02:56 EDT 2008
>Date: Sun, 29 Jun 2008 20:46:32 +0200
>To: Magnus Danielson <magnus at rubidium.dyndns.org>
>From: Predrag Dukic <stijena at tapko.de>
>Subject: Re: [time-nuts] Home built cesium clocks???
>Sure, I will need a lot of help. But the project will have to be long-term.
>I also have a job, and can spare only a couple of hours (or
>less) for this, what is still... a hobby.
>Now I have to stop writing for 3-4 days for those reasons. Next
>time I will elaborate that DDS-FPGA idea a bit deeper.
>At 17:22 29.6.2008, you wrote:
>>From: Predrag Dukic <stijena at tapko.de>
>>Subject: Re: [time-nuts] Home built cesium clocks???
>>Date: Sun, 29 Jun 2008 14:49:13 +0200
>>Message-ID: <18.104.22.168.1.20080629143530.01ed4908 at tapko.de>
>>You have been touching on something that I have been considering for many
>>years, which is also why I have made attempts to learn the field somewhat.
>>I still have alot to read and learn. I had to repair my Cesium and right
>>now I have a second Cesium on the lab-bench.
>>Building my own is still a dream.
>> > One of the requirements for applying for a reference laboratory
>> in Croatia is also to show "scientific excellence" in the area of
>> work (of the lab).
>> > So I'd have to make a some original contribution to the subject
>> and of course to publish it.
>> > It is true that at the moment I need only 250+ optical shift. That with
>> > 9+ GHz achieved through "optical frequency shift multiplication" (apart
>> > from "optical frequency multiplication" which is more difficult)
>> > is one of the ideas that I didn't find reference to in existing
>> > published articles. Something to be explored in the future (see above),
>> > but very interesting, because I could avoid phase noise from SRD
>> > multiplication.
>>This is the benefit of a direct 9 GHz oscillator, which is used in the
>>HP/Agilent/Symmetricom 5071A to reduce wander. The divider chain phase
>>noise still counts in.
>> > Another idea to be tried is to use PREDICTABLE jitter from FPGA DDS as
>> > phase modulation normally used to find the center of the central Ramsey
>> > fringe.
>>Hmm... need to think about that a little. I beleive that the temperature
>>of the microwave assembly counts in. Maybe instead a more elaborate
>>physical stabilisation by means of a control-loop may be something.
>> > DDS achieve desired frequency by slipping reference frequency cycles
>> > from time to time and that way shifting the phase of the output signal.
>> > It is a jitter, but it is not random.
>>I design and use DDS in FGPAs as part of my daytime job. :)
>>The number of bits from the phase accumulator being used for phase to
>>waveform conversion will affect the amount of noise. The commercial
>>cesiums I have seen using DDSes only use I and not I/Q DDSes.
>> > Well thought phase shift/modulation plan can exploit this as phase
>> > modulation.
>>Possibly. I will have to think about it. As I recall it, the shift in
>>Ramsey fringes is due to the phase error between the first and second
>>microwave interigation and the only way to overcome that frequency shift
>>is to run the Cesium beam in the other direction, as I recall it.
>>However, if means to measure the shift can be achieved a control-loop can
>>be built. The trouble is that the detection mechanism does not convey
>>Regardless, let's work together. It is always good to have a few more
>>braincells on the job. Besides, this is what I want to learn more about
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