[time-nuts] Buffering the 1pps output from a Z3801A

[Bruce Griffiths]

Peter Vince wrote:
> Bruce, et al,
>
> 	The 1pps output of an HP Z3801A and Trimble Thunderbolt is 
> only available (as far as I know) as a balanced ECL signal on the 
> 25-pin connector, with dire warnings in the manuals about not 
> earthing either side of the ECL signals.  Would you be able to advise 
> on a simple buffer circuit that would allow me to drive the usual 
> unbalanced 50-ohm coax please?
>
> 	Thanks,
>
> 		Peter Vince  (London, England)
>
>   
Peter

The dire warnings about not connecting the outputs to ground indicate 
that the ECL logic is biased with Vcc ~ +5V(exact supply voltage depends 
on ECL family), Vee = GND.
This is known as PECL (not pseudo  ECL as some would have it, but 
positive (supply) ECL as opposed to NECL - negative (supply) ECL where 
Vee ~ -5V (exact supply voltage depends on ECL family). With NECL 
biasing shorting an ECL output to ground merely reverse biases the base 
emitter junction of the output npn follower, which won't destroy 
anything however no useful output will be produced. When Vcc is +5V then 
shorting the emitter follower output to ground produces a very high 
emitter current which may destroy the output device. Connecting a PECL 
output to ground via a 50 ohm coax termination will cause the output 
device emitter current to exceed its ratings.

If the PECL outputs have suitable pulldown resistors then the 
differential output can be used to drive a twisted pair line terminated 
differentially (ungrounded resistor connected across the line) in its 
characteristic impedance. If the balanced transmission line is short 
(where the maximum length depends on the ECL output transition time) the 
termination may be omitted. The termination can also by omitted if the 
ECL outputs are back terminated with series resistors to match the 
balanced line impedance (provided that the line one way delay is less 
than 1/2 the minimum time between output signal transitions.).

A differential input receiver can be used to translate the differential 
ECL signal to TTL/CMOS levels.
Whilst one can use an RS422 or RS485 receiver, a PECL to ECL level 
translator will add less jitter since it doesnt have a built in 
resistive attenuator.
Since several variants of PECL to TTL translators exist, one first has 
to determine if the outputs are conventional 5V PECL or reduced voltage 
PECL.
This is easy to determine by measuring the PECL output signal levels 
using a high impedance scope probe, failing that even a high impedance 
DVM will work as the ECL output swing is 0.8V or less. Once you've 
determined the PECL supply voltage you can probably obtain PECL/TTL 
translators from Farnell (at least thats where Bilal Amin obtained his 
last year - SY100ELT23ZG for +5V PECL).
The TTL/CMOS output should then be followed by a set of paralleled TTL 
input compatible (eg ACTXX ) CMOS inverters (in the same package with 
small resistors in series with each output to improve current sharing) 
to drive the 50 ohm load (just swap over the PECL (or other differential 
receiver) inputs if the output polarity is wrong. Alternatively if you 
prefer a quieter output stage, one could cascade a couple of long tailed 
pairs, one to drive the 50 ohm load and one to act as input level 
translator, however you will need a +12V 110mA supply for this.

If an RS422 or RS485 differential signal has to be converted to TTL then 
using an RS422 or RS485 receiver is preferable as the RS422 or RS485 
signal levels are not PECL compatible.

It is also possible to use a fast differential comparator to do the 
level translation if nothing else is available. However some care is 
necessary particularly with single supply 5V comparators to ensure that 
the input common mode range isnt exceeded.

Will post circuits shortly.

Bruce