[time-nuts] Updated Divider Jitter Results

John Ackermann N8UR jra at febo.com
Fri Apr 3 22:01:24 UTC 2009

I just finished a jitter test of the first TADD-2 built on the 
production circuit board.

The configuration was somewhat optimized from what I used for the 
earlier tests.

A single 10 MHz source was daisy-chained to the TADD-2 input, to the 
5370B external reference input, and to the 5370B STOP channel.  The 1 
PPS output from the TADD-2 was connected to the 5370B START channel. 
Thus any reference jitter shouldn't be common-mode, and using the 
reference clock on the STOP channel avoids the need for a second 
divider, and ensures that the time interval is small (always less than 
100 ns; in this case, about 90 ns).

For a 10,000 sample run, the standard deviation was 12.1 picoseconds, 
and the peak-to-peak variation was 70 picoseconds.  Based on experiments 
I ran a few years ago, I think this is pretty much the noise floor of 
the 5370B and the divider could be better than this.


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