[time-nuts] time-nuts Frequency Divider
EWKehren at aol.com
EWKehren at aol.com
Sun Apr 5 17:10:24 UTC 2009
Sorry Dave, as I said I am new to the site and am not aware of your work.
Would you please supply me with the link so I can take a look. If the job is
done why all the conversation? Bert
In a message dated 4/5/2009 11:57:33 A.M. Eastern Daylight Time,
david.partridge at dsl.pipex.com writes:
Just another reminder - this job has been done, at least no-one has come
back to me and said "Dave, your divider isn't up to scratch".
Cheers
Dave
-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of EWKehren at aol.com
Sent: 05 April 2009 15:26
To: time-nuts at febo.com
Subject: Re: [time-nuts] time-nuts Frequency Divider
Thank you Bruce for your valuable insight. In the past I did spend time on
Cesium Standards and with valuable inputs from Corby concerning the FTS tube
interface I converted a HP 5062C to a Standard using a FTS tube. I also made
other changes like changing to a 10 MHz 10811, the Master Clock 1 PPS
assembly and the 1 PPS Advance Generator assembly. It has served me well
over the last ten years. Only recently did I get back into the game with
more focus on oscillators, mainly because of the vast accumulation of units
and with Corby's help am looking at oscillators and try to get good short
term as well as long term performance. This is all part of a downsizing
effort. Way to much stuff.
I only recently joined time-nuts and follow the dialog. It is clear that
there is a vast knowledge base that could and probably is used to develop
solutions in this arena and a candidate could be a general purpose divider
chain that addresses most if not all the issues.
Over forty years ago in my college years I did a counter using Motorola MC
790 series and presented a student paper on that subject at IEEE. Did some
more work at home at TI that you can find in old TI Opto Electronics
Catalogs. In this case my contribution would be limited to laying out a PC
board.
Bert
In a message dated 4/4/2009 7:09:00 P.M. Eastern Daylight Time,
bruce.griffiths at xtra.co.nz writes:
Bert
Unless you can provide a set of specifications it isn't possible to
recommend any particular design as being fit for the application.
For the purposes of comparing a divider generated PPS signal against a GPS
derived PPS output almost any input clock shaper should have adequate
performance.
For such applications achieving a sufficiently low jitter PPS output can be
achieved using almost any divider chain.
However ensuring a low clock to output propagation delay tempco is entirely
another matter and either requires a fully synchronous divider or using an
output retiming synchroniser.
If multiple ripple clocking is used in the divider then a 3 stage
synchroniser that first resynchronises to 1MHz, then 2MHz and finally to
10MHz may be required.
If the lower frequency dividers in the cascade use something as slow as
4000 series CMOS then even more synchroniser stages will be required.
If we consider minimising the trigger jitter of an SR620 driven from say a
2V pp 10MHz sine wave, then a single stage limiter with a slope gain of
about 5x and a bandwidth of about 50MHz will ensure that the trigger
circuit jitter due to its linter and trigger circuit input noise is reduced
to below 2ps rms with a low noise input source. If a 2 stage limiter
cascade with the same slope gain is used the jitter due to limiter and
trigger circuit input noise can be reduced to below 1.3ps rms with a low
noise source if the low pass filter time constant at the output of each
stage is chosen appropriately.
If the output of a divider is to be used as a low phase noise source then
picosecond or even subpicosecond jitter is desirable.
For the ultimate performance in such applications a regenerative divider
can have a much lower output phase noise than a digital divider.
Injection locked dividers are one form of regenerative divider complete
with integrated mixer and filter, however conjugate regenerative dividers
using a diode mixer and low phase noise amplifier etc will have lower phase
noise.
Bruce
EWKehren at aol.com wrote:
> Bruce, thank you for the info. I have never had the need or desire to
> get
1
> ps accuracy however in designing low noise signal sources I have
> always
had to
> battle reference oscillator noise and was often nor sure if it was
> the oscillator or the input circuit. However I would like to see a
recommendation as
> to an attainable design. Thanks again Bert
>
>
> In a message dated 4/4/2009 4:35:09 P.M. Eastern Daylight Time,
> bruce.griffiths at xtra.co.nz writes:
>
> Bert
>
> Neither the HP5370 nor the SR620 have low enough internal jitter to
> accurately characterise the intrinisic output jitter of either a
> 74HC04
> (~4ps) or a 74AC04 (~1ps).
> Rather than just tossing together a divider from various parts
> though to produce an output with low jitter its better to be able to
characterise
> the jitter properties (intrinsic as well as that due to logic device
> input noise with a finite input signal slew rate) of various logic
> families.
> It is then possible to actually design a sine to logic level
> converter that achieves the lowest possible output jitter for a given
complexity
> and specified input frequency and amplitude.
>
> The real problem is that one needs to accurately measure jitter of
> 1ps or so.
> There are few time interval counters that allow this.
> One can also measure the change in noise floor when such a device is
> placed in the clock input path of a high frequency ADC and thence
> derive the jitter.
> In principle, the output jitter of a divider can also be calculated
> from the phase noise spectrum of its output.
>
> Bruce
>
>
>
> EWKehren at aol.com wrote:
>
>> Having built eight of Brooks units, my experience was that the
>> problem
was
>>
>
>
>> not with the amplifier but the way the RS F/F in the phase
>> comparator II
>>
> was
>
>> working in some of the devices. For me they all worked in the
>> oscillator
>>
> input
>
>> but some brands did not work properly with the GPS input. With all
>> the
>>
> dialog
>
>> on the divider subject, is it not time to develop one design that
>>
> combines
>
>> KISS and all the collective know how? Bert Kehren WB5MZJ
>>
>>
>> In a message dated 4/3/2009 5:17:18 P.M. Eastern Daylight Time,
>> bruce.griffiths at xtra.co.nz writes:
>>
>> Correction:
>>
>> I forgot to include the intrinsic jitter of the gate in the
calculations.
>> See underlined corrections below.
>>
>>
>> Bruce
>>
>> Bruce Griffiths wrote:
>>
>>
>>
>>
>>> Magnus
>>>
>>> The input noise of a logic inverter or other trigger device used
>>> as a clock shaper is important.
>>> If we have a logic inverter device with the following
characteristics:
>>>
>>> Input noise: 100uV rms
>>> Intrinsic jitter: 1ps rms
>>>
>>> Then the input signal slew rate at the threshold crossing has to be
>>> greater than
>>>
>>> 3x1E-4/1E-12 = 3E8 V/s or 300 V/us
>>>
>>> to ensure that the output jitter isnt increased by more than 5%
>>> from
the
>>> intrinsic jitter.
>>>
>>> With a 1.4V pk 10MHz sinewave input the maximum slew rate is ~89V/us
(at
>>> the zero crossing).
>>> For such an input signal the output jitter will be about _1.5 ps_.
>>> This increases to about _1.72ps_ if there is a threshold offset of
1V.
>>> This can be reduced to about 1.05ps by amplifying the slope of
>>> the
input
>>> signal by ~ 3.4x.
>>>
>>> The intrinsic jitter (RJ. DDJ isn't important when the input signal
is
a
>>> low distortion sinewave) of a 74AC04 inverter is about 1ps.
>>> However the equivalent input noise is unknown.
>>> The noise could, in principle, be determined by measuring the
>>> output jitter as a function of the input signal slew rate.
>>>
>>> Whilst AM and other noise associated with the source can be
>>> reduced by filtering, the input noise of a trigger circuit cannot
(except perhaps
>>> for the trigger circuits input current noise).
>>>
>>> Magnus Danielson wrote:
>>>
>>>
>>>
>>>> Bruce Griffiths skrev:
>>>>
>>>>
>>>>
>>>>
>>>>> Ulrich
>>>>>
>>>>> Your experience with the SR620 illustrates the point I was making
>>>>>
> quite
>
>>>>> well.
>>>>> It really does matter what you do in front of the limiter
>>>>> circuit
built
>>>>> into the counter.
>>>>> A bandpass or any other filter by itself is ineffective unless the
>>>>> signal is exceptionally noisy.
>>>>>
>>>>> By using the inverter in the 74HCT4046 you have added a low
>>>>> gain
>>>>>
> limiter
>
>>>>> stage the bandwidth of which is smaller than that of the SR620
input
>>>>> circuit.
>>>>> This has the effect of increasing the slew rate of the input
signal
>>>>> whilst producing an output with less jitter than the SR620 input
>>>>>
> circuit
>
>>>>> would without this low pass filtered limiter circuit (the
>>>>> inverter
from
>>>>> the 74HCT4046). The slew rate at the 74HCT4046 inverter output is
>>>>> greater than that of the input signal which means that the jitter
due
>>>>> the counter input circuit noise is smaller than when this low gain
low
>>>>> bandwidth limiter isn't used.
>>>>> The input circuit of the SR620 has a wide noise bandwidth (~ 470MHz
>>>>> assuming a single pole response with a 300MHz 3dB high frequency
>>>>>
> cutoff)
>
>>>>> and a correspondingly high total input noise (~350uV rms).
>>>>> If the slew rate of the SR 620 input signal at the trigger point
the
>>>>> jitter due to this noise dominates the trigger circuit output
jitter.
>>>>> The HP5370 time interval counter input circuit has a lower noise
>>>>> bandwidth (~160MHz??) and is quieter (~ 100uV rms) than the input
>>>>> circuit of the SR620 and thus the HP5370 jitter (without the
74HCT4046
>>>>> limiter) for the same 10MHz signal should be less than that of the
>>>>>
> SR620
>
>>>>> (without the 74HCT4046 limiter).
>>>>>
>>>>>
>>>>>
>>>>>
>>>> As a curiosity, there are various variants of the original 4046
which
>>>> has different sensitivity on the input side... one of them has
several
>>>> inverters in a row to get the needed gain where as the other variant
>>>> does not. This difference made a huge difference in some
applications.
>>>>
>>>>
>>>>
>>>>
>>>>
>>> The appropriate device (one that will have the least output jitter)
to
>>> use will vary with the input signal zero crossing slew rate.
>>> That is it depends on both the input signal frequency and amplitude.
>>>
>>>
>>>
>>>
>>>>> If one uses a state of the art trigger circuit with a noise
bandwidth
>>>>>
> of
>
>>>>> 1GHz or more then the total input noise will be even larger so
>>>>> it becomes even more important to use an optimised cascade of
>>>>> limiter+
low
>>>>> output pass filter stages to increase the slew rate of the counter
>>>>> input trigger circuit at the trigger threshold.
>>>>> Careful optimisation of the gain of each stage and the
corresponding
>>>>> output filter cutoff frequency for each stage is necessary to
minimise
>>>>> the output jitter of the counter trigger circuit.
>>>>> There is also an optimum number of such stages that minimises the
>>>>> trigger jitter.
>>>>>
>>>>> The optimisation problem for Limiter stages with gaussian
>>>>> wideband
>>>>>
> input
>
>>>>> noise was solved in the 1990's.
>>>>> Unfortunately the optimum number of stages, associated gains
>>>>> and
output
>>>>> filter bandwidths depends on the input signal frequency and
amplitude
>>>>>
> so
>
>>>>> that in general it isn't possible to use the same limiter
>>>>> cascade
for a
>>>>> wide range of signal amplitudes and frequencies and minimise the
jitter
>>>>> for each frequency and amplitude.
>>>>>
>>>>>
>>>>>
>>>>>
>>>> Actually, you can make a cascade setup which is approaching optimum
and
>>>> insert signal at the stage where the signals slewrate matches
>>>> the
range
>>>>
>
>
>>>> for each stage. Since the gain steps is larger later in a slew rate
>>>> amplifier chain, the last stages may have a little coarse slew rate
>>>> range, but additional mid-range amplifiers that can act as
alternative
>>>> input amps could curcumvent that such that a wide range but and
fairly
>>>> good trigger jitter could be achieved.
>>>>
>>>> The comparator level is fed to whatever stage is the first stage.
>>>>
>>>> Such an approach could lead to much improved jitter values for lower
>>>> frequency signals with associated gain in measurement accuracy.
>>>>
>>>> It is easy to make a pre-amplifier set that achieves this, but
>>>> you
want
>>>> to integrate the control algorithms for automatic use.
>>>>
>>>>
>>>>
>>>>
>>>>
>>> That would constitute an interesting design challenge.
>>>
>>>
>>>
>>>>> Thus such circuits aren't usually employed in general purpose
>>>>>
> frequency
>
>>>>>
>>>>>
>> counters.
>>
>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>> Certainly true. A generic counter is usually equipped with
>>>> triggers
>>>>
> such
>
>>>> that they can measure slewrate without too much difficulty.
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>> However if the input signal frequency and amplitude are known and
>>>>>
> stable
>
>>>>> then using such a limiter filter cascade is feasible.
>>>>>
>>>>>
>>>>>
>>>>>
>>>> Indeed.
>>>>
>>>> Cheers,
>>>> Magnus
>>>>
>>>> _______________________________________________
>>>> time-nuts mailing list -- time-nuts at febo.com To unsubscribe, go
>>>> to
>>>>
>>>>
>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>>
>>
>>>> and follow the instructions there.
>>>>
>>>>
>>>>
>>>>
>>>>
>>> Bruce
>>>
>>> _______________________________________________
>>> time-nuts mailing list -- time-nuts at febo.com
>>> To unsubscribe, go to
>>>
>>>
>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>>
>>
>>> and follow the instructions there.
>>>
>>>
>>>
>>>
>> _______________________________________________
>> time-nuts mailing list -- time-nuts at febo.com
>> To unsubscribe, go to
>>
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>
>> and follow the instructions there.
>>
>>
>> **************Worried about job security? Check out the 5 safest
>> jobs in
a
>> recession.
>>
>>
>
(http://jobs.aol.com/gallery/growing-job-industries?ncid=emlcntuscare0000000
3)
>
>> _______________________________________________
>> time-nuts mailing list -- time-nuts at febo.com To unsubscribe, go to
>>
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>
>> and follow the instructions there.
>>
>>
>>
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts at febo.com
> To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
>
> **************Worried about job security? Check out the 5 safest jobs
> in a recession.
>
(http://jobs.aol.com/gallery/growing-job-industries?ncid=emlcntuscare0000000
3)
> _______________________________________________
> time-nuts mailing list -- time-nuts at febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
>
_______________________________________________
time-nuts mailing list -- time-nuts at febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
**************Worried about job security? Check out the 5 safest jobs in a
recession.
(http://jobs.aol.com/gallery/growing-job-industries?ncid=emlcntuscare0000000
3)
_______________________________________________
time-nuts mailing list -- time-nuts at febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
_______________________________________________
time-nuts mailing list -- time-nuts at febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
**************Worried about job security? Check out the 5 safest jobs in a
recession.
(http://jobs.aol.com/gallery/growing-job-industries?ncid=emlcntuscare00000003)
More information about the time-nuts
mailing list