[time-nuts] femtosecond jitter anyone?

J.D. Bakker jdb at lartmaker.nl
Thu Apr 9 11:46:53 UTC 2009

At 22:03 -0400 08-04-2009, Chris Mack / N1SKY wrote:
>On Apr 8, 2009, at 8:50 PM, Bruce Griffiths wrote:
>>  Chris
>>  If you divide the output down to ~38MHz using a noiseless divider then
>>  the performance is 20dB or more worse than can be achieved with a good
>>  ~38MHz crystal oscillator.
>Ah, this would work, but there is a synchronization aspect since 
>framing on AES/EBU is in the mix (pun intended?) and there are more 
>pieces of external equipment that all need to be synched (within 
>AES11 framing sync margins)...

 From a jitter POV the AES11 profiles are insanely wide, and they make 
little sense if you're not using digital tape or other media which 
take their time to slew to their final speed. Look at the recent TI 
Asynchronous Sample Rate Converters (ASRCs); their rate estimators 
have a bandwidth much tighter than needed to track a worst-case AES11 

>This 38.88MHz is a DSP clock, essentially a microprocessor clock 
>(albeit a very nice microprocessor clock) where the DSP simulates a 
>PLL operating on an incoming clock source, and makes an output clock
>of a different frequency, [...]
>The output of the DSP PLL in this box / design of interest is 11MHz 
>to 24MHz to feed the oversample clocks on the ADCs and DACs, 
>synchronized to the external 44.1kHz to 10MHz master house clock a la 
>the PLL and the rest of the equipment on the other side of the room...

By 'DSP PLL', do you imply that the DSP controls a DDS? If so, is the 
DDS a separate chip or do you use a DAC hooked to your DSP?

For best jitter performance in an audio system you may want to 
consider getting a free-running low noise XO with a frequency that is 
NOT a multiple of your sampling rate(s), have it drive your ADC/DAC 
converter directly and use an ASRC (either integrated or, preferably, 
FPGA/DSP) to go to your target output rate.

As for fs jitter: I've yet to see a converter chip with differential 
clock inputs, and for a single ended clock input I expect that the 
total input-referred noise due to ground bounce &co is in the order 
of a ps, if not worse. (The story changes a bit for discrete 
converter designs, as those can have diff clock inputs with specified 
noise performance).

[all things being equal, voltage pullability == lower Q == more phase 
noise. And that's even before you consider control port noise 
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