[time-nuts] time-nuts Digest, Vol 57, Issue 41

Chris Caudle chris at chriscaudle.org
Thu Apr 23 04:19:39 UTC 2009


I'm a little late following up on this, but hopefully not too out of context.

On Wed, April 8, 2009 10:23 pm, Chris Mack wrote:
> The box / design of interest has ADCs, DACs, and a 38.88MHz OCXO of
> marginal performance coupled with the proposed DSP based PLLs
> generating a local clock for the ADCs and DACs all on the same
> circuit board in synch with external gear.

This sounds like a very complicated way to avoid having to make a PLL. 
Why don't you just use a good quality VCXO in a PLL to sync to the house
clock, and a really low loop frequency, assuming your VCXO phase noise
specs are better than the house clock phase noise at the PLL corner
frequency?

> This 38.88MHz is a DSP clock, essentially a microprocessor clock
> (albeit a very nice microprocessor clock) where the DSP simulates a
> PLL operating on an incoming clock source, and makes an output clock
> of a different frequency, but synchronized to be within AES standards

Yeah, but the out clock is an integer multiple of the in clock, so you
don't really need to jump through synthesizer hoops when a simple divider
in a PLL will do.

I looked at something similar to see if you could save cost by avoiding
the need to have different VCXO's for 44.1k based and 48k based material,
and it is difficult to find off the shelf devices that have suitably low
phase noise and no spurs in the phase noise. I think in the end it
probably ends up being simpler to get the performance you are looking for
by just buying a good VCXO, or two if you need to handle 44.1k and 48k
based material.

> The incoming clock source (master house clock) to this box / design
> of interest is in another rack mount box external to this design on

Have you considered making your box the clock master?  It is easier to
make a low jitter clock which is not pullable, so making everything else
sync to the converter is one way to just avoid a big range of clock
cleaning work.

> Sounds like maybe some LCs to filter out the additional harmonics and
> maybe attempt to get close into the carrier eh?

If you are trying to clean up close in phase noise by using LC filters,
that seems like the wrong way to get there.

Why are you even using an ovenized oscillator to begin with if you have to
synchronize to another clock?  It's not like you care about aging if you
are locking to house sync, your output frequency is just going to be a
multiple of what comes in.  A good quality VCXO should be a lot cheaper
than the $250 you quoted for the ovenized units you were looking at.

> The 12kHz is a figure for the DSP PLL and how they measure it

Because that device is optimized for high bit rate data transfer
applications, where you usually have a high corner frequency on the clock
recovery PLL so that you track source drift and get rid of jitter caused
by ISI.  Basically the opposite of what you want for audio applications. 
This is a baseband sampling application, so phase noise on the sampling
clock is converted to sidebands on the output of the D/A converter, or
encoded as sidebands in the digital output of the A/D converter.  Because
of masking in the auditory system, the sensitivity to sidebands becomes
lower the closer to the fundamental the sidebands are spaced, so you want
very low phase noise from a few hundred Hz up to 30kHz or so, below a few
hundred Hz you care less and less, and above 30kHz you care less until it
causes aliasing in your ADC, but fortunately the phase noise typically
decreases at farther offsets from carrier, so that problem sort of solves
itself.

> sheet with all the other datapoints comes out to 1.3ps  (1Hz to
> 20MHz) of jitter RMS.

Look at 300Hz to 30kHz, that is what you care about.  The 300Hz figure is
arguable, some say as high as 500Hz, some as low as 100Hz.  You can aim
for low phase noise down to 50 Hz if you want to really knock yourself
out.  The current state of the art seems to be the Grimm Audio equipment,
which has a phase noise spec of about -125dBc at 100Hz, and an integrated
noise floor of 2ps above 10Hz.  Not super low compared to some
communications equipment, and that gear is getting raves for audio
quality.
When in slave mode the corner frequency on the PLL is really low, I think
around 0.1Hz.  The claim is that incoming jitter is attenuated 90dB at
10Hz offset, and 60dB/decade above that.
The design still pullable +/-50ppm when in slave mode (meets class 2
requirements for AES11).  Can you get much lower phase noise than that and
still pull across a 100ppm range?  Phase noise and pull range are
inversely related, but I haven't worked out what the theoretical limits
should be for that pull range (I think you should be able to calculate a
limit based on the Q required to give that much pull range).

> I still want to filter such as to distribute a sine...

I didn't understand this.  Usually you want a very fast edge rate so that
the clock input is not affected by noise.  There are times that you want
to keep a sine moving around because you don't want to introduce a lot of
power supply noise from logic output stages switching, but using a logic
output and then filtering it doesn't help there.  I assume when you say
distribute you mean inside the box, right?  So at some point you are going
to have to square up the signal again when you get to the converter chips,
which expect a logic clock, not a sine wave.  What is the point of
distributing as a sine instead of just a square wave?

-- 
Chris Caudle




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