No subject


Sat Dec 19 16:55:59 UTC 2009


There's an oscillator in there to clock the flash (page 2-20). It runs at
around 5 MHz. Need to turn that off. Since standby current is rated at 25ua
it's something that can be done. Low standby also suggests there isn't
anything else nasty sneaking around in there. 

They have four global clocks (page 2-16). Normally they are pretty stable
and free from "stuff".

They have 2 to 4 independently powered output banks (page 2-31). The
isolation between banks is pretty good. Isolation between adjacent cells in
a bank - not so good.  

They will only do single ended I/O (page 2-26). No PECL or LVDS. To get that
you would have to cross over to a Cyclone III FPGA and all of it's issues.

Bob



-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of Ulrich Bangert
Sent: Thursday, February 04, 2010 11:34 AM
To: 'Discussion of precise time and frequency measurement'
Subject: Re: [time-nuts] CPLDs for clock dividers

Luis,

with the help of Bruce I have been trying to put the digital part of a
linear phase comparator (for oscillator characterization) into some
different Xilinx CPLDs. Only to find out that there must be a lot of
"analogue kind" interactions between blocks within the CPLD that had
originally been understood as being purely digital circuitry. I have the
tool chain for ALTERA available as well and I find it highly interesting
that your experience with the MAXII is that good. I will give them a try!
Can you explain a bit what measurement possibilities for jitter you have
available to make these conclusions from?

Best regards
Ulrich, DF6JB

> -----Ursprungliche Nachricht-----
> Von: time-nuts-bounces at febo.com 
> [mailto:time-nuts-bounces at febo.com] Im Auftrag von Luis Cupido
> Gesendet: Donnerstag, 4. Februar 2010 15:21
> An: Discussion of precise time and frequency measurement
> Betreff: Re: [time-nuts] CPLDs for clock dividers
> 
> 
> I understand your arguments...
> 
> I just wonder why reality differs.
> I had a design (GPSDO) that I tested on a FPGA
> (Cyclone) and the same on MAXII and the difference
> was abyssal !!!
> 
> Whatever... the MAXII family has a unbeatable jitter 
> performance compared to discrete logic... That I can tell by 
> direct observation. Other CPLD's I can't tell much only 
> MAX3000 that was slightly worst and MAX7000 that was the same 
> as TTL +/-. Know nothing about Xilinx or others...
> 
> There are so many devices nowadays that I do accept that we
> may no longer set a guideline of what is good or bad in
> general terms anymore.
> 
> Luis Cupido.
> ct1dmk.
> 
> 
> Gerhard Hoffmann wrote:
> > Luis Cupido wrote:
> >> That is not by any means a CPLD. it is a big FPGA and I 
> bet it would 
> >> be doing a bazilon things besides the divider.
> > It shares the CPLD's problems of ground and VCC bounce. The 
> Virtex was 
> > completely empty otherwise and the counter was stoppable, so it was 
> > easy to see the culprit.
> > 
> > Having a hundred ground  pins  should  be more of an advantage and 
> > wether the innards are fine-grained (FPGA) or sum-of-products-cells 
> > (CPLD) really does not matter.
> > 
> > 
> > 73s, Gerhard, DK4XP
> > 
> > 
> > 
> > 
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