[time-nuts] What is the real source of the TBOLT's PPS output?

[Bruce Griffiths]

Magnus

Magnus Danielson wrote:
> Bruce Griffiths skrev:
>   
>> Ulrich
>>
>> The Thunderbolt manual makes it clear that the PPS output is divided
>> down from the 10MHz OCXO output via the CPU and its support circuitry...
>>     
>
> The XC5202 is probably where the 10 MHz to PPS division takes place. I 
> suspect it is also involved in the D/A conversion. Even a naive PWM-like 
> approach to achieve 16 bit would give far higher sample rates than needed.
>
>   
>> If the CPU has an internal PLL and no external resynchronising flipflop,
>> then it is possible that the rms PPS jitter may be as high as 300ps or so...
>> A gate array with insufficient ground and Vcc pins could also have a
>> similar output jitter. The jitter produced by whatever circuitry is used
>> to shape the OCXO output into a logic level square wave can also
>> contribute significant jitter if the signal amplitude is relatively low
>> at the input to the shaper.
>>     
>
> I did some probing around...
>
> The transistors sitting under the OCXO amplifies it and a logic gate 
> converts it into CMOS levels.
>
>   

What is the signal amplitude at the input to this logic gate?

If this signal is say 2V pp then as little as few tens of mV rms  of
supply noise on this logic gate may be enough to produce the observed
jitter.
I measure about 300ps rms (100 sample average) jitter of the PPS signal
wrt the 10MHz signal zero crossing.
However my Thunderbolt is powered by a switching power supply.
Another potential source of noise is the OCXO power supplies, however
this should largely cancel out when measuring the PPS to 10MHz jitter.


> The CPU and correlator-chip has a 18,432 MHz clock which is locked to 
> the 3,6864 MHz oscillator. It could be the same correlator chip used in 
> the Lassen receiver or somewhat earlier. It is not clear from the 
> material I have, but it kind of looks the same at least. It surely has a 
> PPS on one of the pins which could be usefull to bootstrap the 10 MHz 
> derived PPS.
>
> Anyway, the 18,432 MHz is a logical frequency as the 85th multiple will 
> mix down to 8,7 MHz which is then probably sampled by 3,6864 to produce 
> a sampled intermediary frequency of 1,332 MHz which is just what you 
> want to hit the digital channels in a C/A correlator chip.
>
> This is the clock also being compared to the GPS. It could be that the 
> 10 MHz is used to lock up the 3,6864 MHz clock. Not entierly impossible, 
> but I am skeptic. But wait... the DFF sitting there (74AC174 has a nice 
> little 9765,625 frequency humming about it. This is 10 MHz divided by 
> 1024. However, it does not seems to lock up the 18,35 MHz (which is what 
> I read off it...).
>
>   
>> The solution for your purposes is to use a resynchronising flipflop to
>> remove this jitter before making your phase error measurements within
>> your external OCXO discipling circuitry.
>>
>> Bruce
>>
>>
>>
>>
>> ________________________________
>> From: Ulrich Bangert <df6jb at ulrich-bangert.de>
>> To: Time nuts <time-nuts at febo.com>
>> Sent: Saturday, 24 January, 2009 4:21:10 AM
>> Subject: [time-nuts] What is the real source of the TBOLT's PPS output?
>>
>> Gents,
>>
>> considered an OCXO with an OAVAR of or better say 1.0E-11 @ 1 s (as used
>> in the TBOLT) and a divider chain to generate an 1PPS from the 10 Mhz
>> oscillator signal. What OAVAR @ 1 s would we expect if we compare the 10
>> MHz to the PPS derived from it? 
>>
>> I know, the answer is not given easily, but: If the divider chain is
>> engineered correctly (i.e. a synchronous and not a ripple divider) then
>> we are basically comparing the 10 Mhz with a delayed version of itself.
>> The delay will be the typical clock-to-output propagation delay of a
>> d-flipflop of the dividers chain's semiconductor family. 
>>     
>
> The DFFs available (74AC174) are clocked with the 10 MHz clock and I 
> have a pair of 9765,625 Hz signals there. I need to dig around more.
>
> The Xilinx XC5202 has the 10 MHz on its clock input and outputs the 
> divided down variant 9765,625 Hz and I suspect also the PPS even if it 
> has not been located. The 74AC174 sits just next to it, so it is not 
> impossible it is there for clean-up tasks.
>
> Cheers,
> Magnus
>
>   

Bruce