[time-nuts] state of the art devide by ten
bruce.griffiths at xtra.co.nz
Mon Mar 30 12:04:58 UTC 2009
Do you mean one should use SiGe ECL (or CML) D flipflops or higher
performance devices for the output synchronisers?
It would surely be a little difficult to justify this given the
relatively noisy outputs of most rubidium sources.
A 74HC4017 has a symmetric 1:1 mark space ratio divide by ten output.
So in this respect its just as suitable as a 74XX90 for this task.
EWKehren at aol.com wrote:
> In my opinion the best way is still to use two 74xx90 connected divide by
> five and divide by two. That gives a symmetrical output. That is why you can not
> use a 390. The A output should subsequently be applied to a D or JK flip
> flop with the clock input connected to the 10 MHz. The D or JK F/F should be as
> fast as what is presently still available.
> Bert Kehren Miami WB5MZJ
> In a message dated 3/30/2009 1:10:57 A.M. Eastern Daylight Time,
> hmurray at megapathdsl.net writes:
>> What would be a "through the hole" type of IC that would have less
>> jitter than a 74xx90. I CAN do surface mount if I have to.
> In general, I think faster logic families have lower jitter. I'm not sure
> could prove that or find a good paper. There may be counter-examples.
> If you want low jittter, I think the right approach is to divide by X/2 and
> then do the final divide by 2 in a separate chip. There are several logic
> families that have only one gate or one FF in a package. They are usually
> SMT, typically SP-23 type packages with fairly big pins so hand soldering
> with old-fart eyes is not that hard.
> Prop time with multiple outputs in a package depends on how many outputs are
> switching. In the case of a divide by 10, the pattern is stable. If you
> look at the divide by 2 output pin, I'd expect more jitter since sometimes
> lower order bits are switching and sometimes they are not.
> Another approach is to use a CPLD. Clock the main divide by 10 or 100 on
> wrong edge, and then buffer the final output on the right edge. Some CPLDs
> are targeted at low power. It'd expect them to have more jitter than the
> ones targeted at high-speed. There may not be much choice.
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