[time-nuts] On low-voltage TAC/TDCs for a GPSDO

J.D. Bakker jdb at lartmaker.nl
Thu Aug 12 22:45:23 UTC 2010


Hello all,

I'm working on Yet Another DIY GPSDO, and one of the issues I've been 
looking into is a TAC/TDC to do sawtooth correction on the 
measurement of the GPS PPS signal. I'd like to stick with a 3.3V 
supply for most of the circuit, and several of the TAC designs that 
have been discussed here in the past run into trouble at such low 
voltages (mostly through VBE drops).

To start with the context: I'm planning to use a microcontroller with 
a built-in dual 12-bit 2MSPS ADC. I'd like to not use anything that's 
not available at Digi-Key or Mouser, and keep the SMD pitch >=0.8mm 
(with a possible exception for dual transistors in SOT-23-6). That 
way the design shouldn't be too hard for others to replicate.

I'm aiming for a TAC accuracy of 1ns, allowing for one or a few 
calibrations between PPS pulses. Minimum full-scale range should be 
+/- a few hundred ns, to allow for outliers. (The plan is to have an 
initial FLL for coarse locking, and have the PLL kick in after that). 
I'm penciling in an ADC reference voltage of 2V, as that's commonly 
available and leaves enough headroom to use the current sources in 
their most linear range.

I've attached a diagram that reflects a few of my current thoughts.

- Circuit 1 is the traditional TAC. Before the start of the cycle Q2 
conducts, discharging C1 and shunting I1's current to ground. At this 
point the ADC can measure the voltage drop across C1/Q2 to eliminate 
that offset. Taking nSTART low puts Q2 into high-impedance, and I1 
charges C1 through D1 until STOP is raised causing Q1 to shunt I1's 
current to ground. At this point the ADC samples the voltage across 
C1, which is proportional to the time between START and STOP (modulo 
offset and nonlinearities).

This circuit is well known to work (although it is more common to use 
Q1 for both START and STOP and to limit Q2 to ramp discharge duties). 
Downsides are that negative time offsets cannot be measured directly, 
and the constant output voltage offers little room for increased 
precision through sample averaging, unless the ADC's input noise is 
large compared to its LSB size. For the same reason there is no easy 
way to reduce the effects of ADC INL/DNL.

- Circuit 2 works in a similar way, except that the ramp isn't 
terminated by a STOP signal but is allowed to run freely until I2 
saturates. The ADC is set to sample continuously, taking multiple 
samples of the ramp, and the microcontroller interpolates the 
resulting values to determine the elapsed time between an internal 
time reference point and the START signal.

This circuit is fairly simple, and has the advantage that there is no 
hard limit to its range. Curve-fitting the sampled values increases 
precision and reduces the effects of INL/DNL. On the other hand, ADC 
aperture jitter and offset have a direct impact on resolution.

- Circuit 3 expands on this approach by having dual ramp generators, 
and having the ADC measure the voltage difference between the two.

This approach is the only one of the three that can directly measure 
negative time offsets, allowing a regenerated pulse to be directly 
compared with the GPS' PPS. A small difference in ramp rates, 
unavoidable in practice, actually helps to average out DNL and is 
easily corrected in calibration. Sampling time uncertanties have less 
impact than in Circuit 2. Then again, it may be difficult to reliably 
detect the start/end-of-ramp points from the samples alone. Total 
range is relatively limited, and due to the differential measurements 
it is harder to reduce current source nonlinearities in software.

Any thoughts? At this point I'm tempted to build a hybrid of 2 and 3, 
using one of the microcontroller's ADCs in each mode.

I've not seen prior work on the ramp-approach, although it's a close 
cousin to the centroid pulse timing method 
(<http://www.febo.com/pipermail/time-nuts/2006-September/021765.html>). 
Has anyone seen it before (and possibly shot down due to major 
deficiencies)? It seems too obvious to not have been considered by 
others.

(Notes: These are initial rough sketches. The ramp current has not 
been optimized yet; I have an unsubstantiated feeling that 
brute-forcing it with a higher current and larger cap may well help 
to swamp some of the nonlinearities. I've mostly picked 1V/us ramp 
speed out of the air because it gives me 4-5 samples @2MSPS which is 
a workable number to do curve fitting on. Also not sure whether I'll 
use the simpler one-transistor current source or the hi-Zout mirror 
with a current source derived from the ADC's reference. The FETs may 
end up being implemented as single-gate /OE drivers. I'll do a more 
complete write-up on the entire GPSDO later).

Thanks,

JDB.
-- 
"There is a style of design I call "wishful thinking engineering."  It starts
  with something like "pigs can fly if you feed them enough beans" and develops
  utopian plans such as like having everyone commute to work riding on personal
  pigs, and along the way ignores minor details such as the consequent rain of
  the non-gaseous byproducts."

  (Vernon Schryver in n.a.n-a.e)
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