[time-nuts] Advice on 10 MHz isolation/distribution

[David C. Partridge]

In the Frequency Divider design I did back in 2008, I used 4 outputs from a
74AC541 in parallel for each output frequency, with a 180 ohm resistor in
series with each output.  Unused inputs were of course tied to ground.
Output impedance of each driver in the '541 should be around 20-25 ohms, so
the whole ensemble should give about 50 ohms output impedance (certainly
when loaded with 50 ohms, the output voltage was almost exactly 2.5V).

With this setup you can safely short the output to ground with no damage
(max draw per output pin of about 25mA which is half the maximum rating of
50mA per output pin).

Using a four layer board (power and ground planes), I didn't see much sign
of ground bounce, just some overshoot on the 0V to 5V transitions.

Dave

-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of Bob Camp
Sent: 19 February 2010 17:30
To: 'Discussion of precise time and frequency measurement'
Subject: Re: [time-nuts] Advice on 10 MHz isolation/distribution

Hi

Yup, that works. 

A couple of *very* minor points:

-------------

My guess is that your output stage will be pulling a bit more than 15 ma.
This assumes you are running a 50 ohm load and a 50 ohm output impedance to
deliver 13 dbm (~ 2.5 V p-p). 

More or less, 100 ohms from +5 to ground would be 50 ma half the time. The
stage likely will pull 25 or more ma. (Says Bob who hopefully hasn't done
any typos in the last minute or so). 

You might also want to parallel two (or more) gates to get the output
current into the "safe" region. 

--------

The Datum LPRO manual on page 18 shows some data for AC gates driven with
very simple circuits (just bias the gate ...). The data they show would be
adequate for the proposed application (if I remember the numbers right).
Power supply bypassing is indeed an issue no matter how you do this.

--------

AC gates create some *major* supply line spikes. Depending on how you look
at ground bounce, it might be an issue in terms of isolation. Good layout
practices required....

--------

The gate approach also lets you generate an "almost differential" signal
without a lot of crazy effort. One 74AC86 should do the trick. 

--------

Not real sure that Clay is a big fan of lots of harmonics or of filters. 


Bob



-----Original Message-----
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
Behalf Of Garry Thorp
Sent: Friday, February 19, 2010 10:18 AM
To: time-nuts at febo.com
Subject: Re: [time-nuts] Advice on 10 MHz isolation/distribution

Hello Clay,
 
Joining in this discussion at a rather late stage  -  have you considered
using 74AC series gates as buffers? They provide reasonable isolation and
have surprisingly low phase noise.
 
A single 74AC04 inverter gives over 40dB reverse isolation at 10MHz, so
3 cascaded gates would give more than enough. You would need to use a
separate IC for each stage to achieve the isolation, but they are cheap!
With a series output resistor, a 74AC gate with 5V supply will give ~13dBm
while providing a 50R source match. Adding a series tuned circuit will give
a sine wave if required. At 10MHz the first 2 stages will draw ~2mA and the
output stage ~15mA (as a matched 50R source), so the necessary isolation
between power supplies can readily be achieved by using separate RC filter
chains to each IC.
 
I haven't measured the phase noise of an AC04, but I have tried dividing a
low-noise 100MHz OCXO using a 74AC163. At 100MHz, the OCXO's phase noise was
~-80dBc/Hz at 1Hz offset, -110 at 10Hz, -140 at 100Hz, ~-166 at 1kHz and
~-180 at 10kHz and beyond.
Taking the Qc output of the AC163, the phase noise at 12.5MHz showed the
theoretical 18dB reduction at low offsets, i.e. ~-98 at 1Hz and -128 at
10Hz. It then went into a flicker of phase region, ~-155 at 100Hz and
-165 at 1kHz, reaching a floor of ~-178dBc/Hz by ~100kHz offset.
 
Extrapolating the flicker region downwards suggests the divider output phase
noise would be ~-145 at 10Hz and -135 at 1Hz. Intuitively, I wouldn't expect
an inverter to have worse phase noise than a counter from the same family.
Cascading 3 inverters would increase the flicker phase noise by ~5dB, which
I think would still be well within the spec you gave earlier. This approach
has the advantage that it can be done without transformers or inductors
(unless you need a sine wave output).
 
Digital inputs need a high slew rate to achieve low phase noise, so if your
oscillator has a sine wave output you would probably need to square it up
with a (non-saturating) limiter such as a common-base driving into a
Schottky diode limiter, or a long-tailed pair.
 
As CMOS is a saturating logic family, low-noise power supply is vital.
The input switching threshold is approximately half the supply voltage, so
supply noise + non-infinite slew rate = jitter. The lowest-noise LDO
regulators are probably not good enough. However this is a (relatively!)
straightforward low-frequency problem, that can be solved by using a heavily
filtered voltage reference with a low-noise op amp buffer or Darlington
emitter follower.
 
Garry
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