[time-nuts] Advice on 10 MHz isolation/distribution / PhaseNoise of 74AC gates

[John Miles]

Hi, Garry --

> I knew from other people's measurements that 74AC was capable of better
> than -160dBc/Hz when used to make a phase detector at 10MHz, but I
> wanted to do a quick feasibility check on a divider for an application a
> couple of years ago.
>
> The 74AC163 was powered from a linear bench supply via a long (many
> seconds) RC time constant plus local decoupling. I adjusted the supply
> to give 5V at the IC when it was operating.
>
> The 100MHz OCXO, which gave 18dBm into 50 ohm, was AC-coupled into the
> clock input, which was biased to half the supply voltage. The counter
> was left dividing by 16, as its propagation delay and set-up times are
> too long to programme it to divide by 10 with 100MHz clock rate. The
> output was AC-coupled directly to the E5052B input, without any
> filtering. I had to use the Qc output as the SSA doesn't work below
> 10MHz.
>
> The attached plot shows the 12.5MHz phase noise plus that of the 100MHz
> OCXO. The divider phase noise tracks 18dB below the OCXO at low offsets
> as expected, before its flicker noise and eventual noise floor
> predominate. I was primarily interested in seeing what the flicker noise
> was like, but I was surprised when I saw how low the floor was!
>
> The E5052B does the necessary calibration automatically before doing a
> measurement - from my experience with the instrument I have no reason to
> doubt the validity of the result. (The indicated 100MHz phase noise in
> the ~1-50kHz region is actually limited by the E5052B, owing to my
> setting only 100 correlations. However it shows it low enough to
> indicate that the CMOS noise dominates over that range.)
>
> I realise that a divider is very different from a simple inverter, but I
> think this gives an useful indication of what AC logic is capable of.

Some interesting results, all right.  The 74AC parts do seem to be quite
decent in the PN department.  To try to corroborate your observations I ran
some residual PN tests on a 74AC04 inverter using a different measurement
technique (splitter+quadrature delay line): see http://www.ke5fx.com/ac.htm
.

While I didn't achieve anything like the broadband floor you saw, I did find
that the close-in noise was quite a bit better than your E5052B plot showed.
It doesn't seem correct to blame your 1/f^3 slope below 1 kHz on CMOS
process noise, as it doesn't show up in a true residual test.  That is more
likely to be your OCXO's PN profile, improved 18 dB by 20*log(N).  It looks
virtually identical to a couple of Wenzel parts I measured awhile back
(attached).

I agree that an edge conditioner and a clean Vcc supply could wring some
serious performance out of these chips.  The power supply might account for
the broadband-floor deficit relative to your test setup; I'm not really sure
what to expect there.  I made some PSU noise measurements awhile back but
the methodology was pretty bad and I don't really trust my results.  Will
try to do some more in-depth tests later, to see what's really possible.

-- john, KE5FX
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