[time-nuts] Basic question regarding comparing two frequencies

[EWKehren at aol.com]

Hi,
 ten years ago not having a super counter I copied the input circuit  of 
the Austron 2110 that using an XOR gate mixes 5 MHz with 500 Hz getting  
5.0005 MHz. It is devided down to 1.0001 Mhz which in turn is mixed in 74 HC 74  
D F/F giving 100 Hz, that most counters are able to count at high 
resolution.  Still use it today. May be a time-nuts project.
Bert Kehren
 
 
In a message dated 7/26/2010 2:15:57 A.M. Eastern Daylight Time,  
bruce.griffiths at xtra.co.nz writes:

Hal  Murray wrote:
>    
>> There is another way to  compare two frequencies, relevant when they   
are
>> very  close together. I divide a reference down to 100KHz and use it to  
clock
>> a phase detector made of a pair of D flip flops. The unknown  (divided to
>> 100KHz) is fed into the circuit and an  output   that is proportional to 
the
>> phase difference  appears on the output as a changing mark-space ratio.
>>     
> I like it.  Thanks.
>
> How did you pick 100  KHz?
>
>    
>> Using CMOS and a precise power  supply (because under no load, CMOS
>> output is precisely rail to  rail), the averaged output (100ms RC 
filter) is
>> fed to a strip  chart recorder.
>>      
> Has anybody checked  the edge cases and/or linearity of a setup like this?
>
>   
>> The recorder shows the changing phase difference and folds  back each 
time
>> a whole cycle passes. A 12 bit analog data logger  resolves 2.5ns of 
phase
>> and gives data for further  analysis.
>>      
> Is 2.5 ns good  enough?  What would you gain by using a 16 bit DAC?
>
>   
A ratiometric ADC where the ADC uses the (low pass filtered) CMOS  supply 
as its reference is probably advisable when using high resolution  ADCs.
A high resolution sigma delta ADC that aloows an external reference  to 
be used may be useful for this  application.
>
>
>
>
> If 2.5 ns is good enough,  I'll bet you can do the whole thing in digital
> logic.  Just get a  fast FPGA/CPLD.  I haven't done a serious design, but 
a
> quick  check at some old data sheets shows it's not silly.  You could  
probably
> bump it up by another factor of 2 with some external (p)ECL  chips.
>
>
>    
If one used an FPGA with an  internal 500MHz (use the internal PLL 
available in some FPGAs) clock and  dual edge clocking or a 1GHz internal 
clock, 1ns resolution should be  readily achievable. However it may be 
advisable to use something like LVDS  inputs to alleviate the effects of 
ground and Vcc bounce.
If you need  more resolution then one could always sample the outputs of 
an internal  tapped delay line using internal gates as delay elements.
With a suitable  FPGA a resolution of a few hundred ps is feasible.
If the delay line delay  is more than 1 clock period then an embedded 
calibration of the delay line  is possible from the coarse (1ns) count 
and the fine count from the  internal tapped delay  line.


Bruce


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