[time-nuts] Tight-PLL - YOU DON'T NEED TO READ IT IF YOUR FED-UP WITH THE THREAD SO HIT DELETE NOW!

[Steve Rooke]

On 5 June 2010 19:07, Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:
> Wrong again.

No, I'm not wrong Bruce.

> The integration/averaging referred to occurs when one counts the output
> transitions of the VFC for a fixed time interval.
> This process needs to be replicated using the sampled EFC data if one is to
> measure ADEV.

This process is exactly replicated by oversampling the EFC and
determining the average for a fixed time period.

If you can't see that this performs exactly the same function, I don't
know what will convince you.

Steve

> Bruce
>
> Steve Rooke wrote:
>>
>> I think I have found the source of the "integration" issue. I've spent
>> some considerable time ploughing through as many sources of
>> descriptions on ADEV, AVAR and the tight-PLL method. I've even tried
>> looking for the infamous "finite time interval integrator" which seems
>> to be highly notable by it's complete absence on Google. Well,
>> eventually the answer struck me directly in the eye, the source of the
>> integrate issue comes directly down to the original paper that Warren
>> posted a link for:-
>>
>> D. Tight phase lock loop method
>>
>> The second type of phase lock loop method (shown in figure 1.7) is
>> essentially the same as the first in figure 1.6 except that in this
>> case the loop is in a tight phase lock condition; i.e., the response
>> time of the loop is much shorter than the sample times of
>> interest--typically a few milliseconds. In such a case, the phase
>> fluctuations are being integrated so that the voltage output is
>> proportional to the frequency fluctuations between the two oscillators
>> and is no longer proportional to the phase fluctuations (for sample
>> times longer than the response time of the loop). A bias box is used
>> to adjust the voltage on the varicap to a tuning point that is fairly
>> linear and of a reasonable value. The voltage fluctuations prior to
>> the bias box (biased slightly away from zero) may be fed to a voltage
>> to frequency converter which in turn is fed to a frequency counter
>> where one may read out the frequency fluctuations with great
>> amplification of the instabilities between this pair of oscillators.
>> The frequency counter data are logged with a data logging device. The
>> coefficient of the varicap and the coefficient of the voltage to
>> frequency converter are used to determine the fractional frequency
>> fluctuations, yi, between the oscillators, where i denotes the ith
>> measurement as shown in figure 1.7. It is not difficult to achieve a
>> sensitivity of a part in 1014 per Hz resolution of the frequency
>> counter, so one has excellent precision capabilities with this system.
>>
>> http://tf.nist.gov/phase/Properties/one.htm
>>
>> The relevant section here is "the response time of the loop is much
>> shorter than the sample times of interest--typically a few
>> milliseconds. In such a case, the phase fluctuations are being
>> integrated so that the voltage output is proportional to the frequency
>> fluctuations". So what this says is that by incorporating a PLL-loop
>> filter that has a B/W much wider than the sample time, the phase
>> fluctuations are integrated into the reference oscillator such that
>> the control voltage of the tight-PLL now reads frequency which is
>> unlike the loose-PLL which directly records the phase relationship
>> between the oscillators. So the term "integrated" here is used a verb
>> and not a noun, therefore it is an intrinsic function of the design
>> not a separate process.
>>
>> Steve
>> --
>> Steve Rooke - ZL3TUV&  G8KVD
>> The only reason for time is so that everything doesn't happen at once.
>> - Einstein
>>
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>
>
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-- 
Steve Rooke - ZL3TUV & G8KVD
The only reason for time is so that everything doesn't happen at once.
- Einstein