[time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz
SAIDJACK at aol.com
SAIDJACK at aol.com
Wed Mar 10 18:36:11 UTC 2010
Hi Ulrich,
I think in our design the spec is limited by the ~-100dBc noise at 100Hz
offset of the 100MHz VCXO.
Please note that the ADF4002 actually improves that noise by about 15dB
from the datasheet spec (or the unit we tested was that much better than the
one shown in the datasheet).
Also, the ADF4002 allows different Current settings for the PFD, this
affects phase noise as well. Fine-tuning of these settings and the loop filter
reduced the noise further. We use a 10MHz PFD output, so that should be
optimal for phase noise.
So in short, we improve the inherent close-in PN performance of the VCXO
significantly. Would an Exor gate have resulted in better performance? Maybe.
But the 10MHz spur on the VCXO EFC pin from the EXOR output may cause much
higher spur levels at 10, 20, 30MHz etc on the VCXO output. And you would
have to contend with counter noise (10:1 divider), and there would not have
been flexibility in frequency, as well as a PLL Lock indicator..
bye,
Said
In a message dated 3/10/2010 07:19:14 Pacific Standard Time,
df6jb at ulrich-bangert.de writes:
Let me put forward the question in another way: Had you to lock a 100 MHz
VCXO to a 10 MHz reference, what other chip had you used that you believe
is
the better performer? Please no injection locking or even stranger, just
plain PLL.
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