[time-nuts] Divider pecking order ?
Magnus Danielson
magnus at rubidium.dyndns.org
Mon Mar 22 00:38:26 UTC 2010
Bruce Griffiths wrote:
> The performance of the sine to square wave conversion clock shaper
> circuit may dominate the divider performance.
> Thus an evaluation of the jitter performance of sine to square wave
> conversion circuits would also be informative/useful.
We should standardise some test for estimating the input contribution.
I would prefer using various amplitudes, preferably with a measurement
of achieved slew-rate.
> If one is using a digital divider in a narrow band PLL the close in
> phase noise performance of the divider may be more important than its
> phase noise floor, in which case an ECL or CML divider (or at least a
> divider using a CML or ECL resynchronising flipflop) may be a better
> choice than a TTL or CMOS divider, especially if a low noise diode
> mixer is used as a phase detector is used.
I have reason to beleive that pulse-width factor has great importance in
the produced result for mixer-based measurements. I have not had the
time to make any conclusive measurements or theoretical work for it, it
just looks like that.
> Thus characterising divider phase noise may also be useful, although
> it may be difficult to do this for divider output frequencies much
> below 1Mhz or so.
Indeed.
It's a pitty that the SIA-3000 stops doing meaningful measurements at 11
MHz... and lower. If someone could tell me how to overcome that, I would
be very greatful.
Cheers,
Magnus
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