[time-nuts] 10MHz to 80MHz frequency multiplier suggestions

[Bruce Griffiths]

Whilst the close in phase noise of the ADC used in the TSC5115 may be 
comparable with that of a 74AC04 the phase noise floor of such ADCs is 
degraded when clocked by a 74AC04:

http://www.analog.com/static/imported-files/seminars_webcasts/High%20Speed%20System%20Applications%20%28PDF%29/HS%20Systems%20Part%202%20for%20Print_A.pdf

http://www.analog.com/static/imported-files/application_notes/5847948184484445938457260443675626756108420567021238941550065879349464383423509029308534504114752208671024345AN_756_0.pdf

http://www.analog.com/static/imported-files/application_notes/57206466474685142207552745732150239440755569051663372515871138132239AN_835_0.pdf

http://www.analog.com/static/imported-files/application_notes/59756494064912342505447175991257024546937062255921511183854180687755AN501_a.pdf

In particular such ADCs have been be used to measure the jitter of 
various logic families by using devices from the logic family to drive 
the ADC clcok /encode inputs and comparing the increased noise floor 
with that when the ADC clock/encode inputs are driven with a bandpass 
filtered low phase noise sine wave.

Bruce

John Miles wrote:
>    
>> Before one can conclude such a solution is adequate one needs to know
>> the ADC requirements for clock jitter.
>> If the ADC is a high resolution pipelined ADC like those available from
>> AD and LTC then such a solution will degrade the performance
>> significantly.
>> These ADCs require clock cycle to cycle jitter of a few tens of femtosec
>> or less to realise the datasheet performance.
>>      
> Actually it's better (worse?) than that, for two reasons: 1) none of those
> ADCs can take advantage of a clock noise floor much better than -150 dBc/Hz,
> and 2) the clock noise is improved by 20*log(clock/input).  That means an HF
> receiver like the Perseus will be able to shrug off some or all of the noise
> added by the multiplier, depending on where you tune it.
>
>    
>> The intrinsic jitter of an ACMOS gate is too high by a factor of
>> 20 or more.
>>      
> For an HF source, -133 dBc/Hz is a very small amount of phase noise at 1 Hz.
> For comparison, both the HP 10811 and later-model Thunderbolt OCXOs are in
> the -100 to -110 dBc/Hz neighborhood at 1 Hz.
>
> The residual PN of a 74AC04 is about -135 dBc/Hz at 1 Hz, measured on a 10
> MHz carrier(1).  The TSC 5115A, whose ADCs are from the same basic family as
> the one in the Perseus, has a (non-correlated) 1-Hz measurement floor
> of -133 dBc/Hz(2).
>
> Bottom line: if you use reasonable construction practices and maintain a
> high signal level throughout the chain, I don't think there is much to worry
> about when driving an ADC with a 10 MHz->80 MHz multiplier.  I would worry
> more about spurs than noise.
>
> (1) http://www.ke5fx.com/ac.htm
> (2) http://www.symmetricom.com/link.cfm?lid=6156
>
> -- john, KE5FX
>
>
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