[time-nuts] Frequency multiplication

[jimlux]

On 2/5/11 10:20 PM, Tijd Dingen wrote:
>>> You don't feed the ADC from the FPGA if you can avoid it.
>
>> especially if your ADC clock is a different frequency from the processor
>> clock that's being used for most of the other logic on the FPGA.  I'd
>> give a ballpark estimate of 20-30 dB isolation between the two on a
>> Virtex 2.
>
> I read and reread that part...
>
> Hopefully you mean this along the lines of: should you decide to feed two
> different clocks into the Virtex-2, and use the dedicated global clocks, then
> you guess the isolation between those 2 global clock lines to be on the order of
> about 20-30 dB. So basically...
>

No guessing.. I've measured it, albeit indirectly.  I feed a sine wave 
into the ADC being driven by one clock (from the FPGA) collect a bunch 
of samples, and you can see the spurs from the clock jitter when you run 
a power spectrum.  The spurs move as expected when you change either 
clock frequency.



> Do NOT:
> - feed crappy clock A into fpga
> - feed precision clock B into fpga, let it go through the PLL, and route the
> resulting clock C outside the fpga again.
> - use clock C as clock source for your precision DAC.
>
> Do however:
> - feed crappy clock A into fpga
> - feed precision clock B into fpga, let it go through the PLL, and only use it
> internally.
> - use clock B as clock source  for your precision DAC.

That would be the preferable approach, however, if you want to be able 
to change the frequency of clock B (or turn it on and off) that gets tricky.

I note that clock A could be a mighty fine clock too.. it's the clock 
leakage.

>
> ... if not I am probably missing something.
>
> Apart from that, with the push for higher and higher bitrates, even the onboard
> PLL's are now becoming "reasonable" for the less demanding applications. However
> I suspect that for the more demanding applications an external pll will still
> remain the way to go for some time. For my DIY counter project I use a
> spartan-6, which has a decent enough serdes (and the PLL that goes with that),
> but I won't let the fpga generate the higher clock rate. I'd rather do that with
> an external PLL. Maybe when the new 28 nm fpga's from xilinx/altera have good
> availability in a year or two... Then again, ADI&  co won't sit still for those
> two years, so who knows. ;)
>

yes..

In my particular world (space flight hardware), we tend not to use the 
latest and greatest components, so techniques that have been overtaken 
by events in the commercial world have a lot of value.

We joke about getting questions in design reviews about why we're not 
using the tried and true and flight proven 12AX7 dual triode rather 
these new fangled transistor thingies.  After all, we've got the triodes 
in flight stores, ready for use.

But really, we tend to run about 10 behind state of the art components 
(today we're using Virtex IIs and AX2000s.... New designs are 
considering Virtex 4 and 5)