[time-nuts] 5370 firmware hacking status report

[Bruce Griffiths]

Poul-Henning Kamp wrote:
> In message<77E0FBA5-AA78-4399-9562-D1274E109AF4 at jks.com>, John Seamons writes:
>
> I would worry a bit about the PLL locking too, but I have no idea how
> to actually measure it.
>
> I think the 1sec max gate-time is related to the eventcounter width,
> but it might be possible to simulate a wider counter in software.
>
> The obvious idea for advanced functionality is calculation of
> allan deviations
>
>    
The PLL sample frequency is around 0.8MHz so that trigger rates 
approaching this will alter the PLL loop parameters.
Trigger rates greater than the PLL sample frequency (200/256MHz) will 
likely cause lock to be lost.
The 5359 (uses the same vernier oscillator assembly) overcomes this by 
using a digital sample and hold  to set the VCO control voltage.
However periodic auto calibration by closing the loop is required to 
avoid drift.

Bruce