[time-nuts] time interval with 10 ps resolution using cheap FPGA ?

Tristan Steele tristan.steele at gmail.com
Fri Mar 11 05:46:31 UTC 2011


I can't really add much to the questions - but I am very interested in the
answer!

Tristan

On 11 March 2011 16:33, beale <beale at bealecorner.com> wrote:

> I was interested to see this 2009 Fermilab paper which claims a 10 ps (RMS)
> timing resolution in a TDC (time to digital converter) implented in the
> Altera Cyclone II FPGA, which of course has a much slower clock than that.
>  They call their technique a "wave union TDC", involving multiple readouts
> of an internal ring oscillator triggered by the input signal, permitting
> calibration of the relatively coarse and uneven delay elements in the FPGA.
> http://lss.fnal.gov/archive/2009/conf/fermilab-conf-09-275-e.pdf
>
> I have not worked with them yet, but there are some pretty cheap FPGA
> development boards now-, for example, at the $50 price point for a fully
> assembled "Papilio One" board (hosting a Xilinx Spartan 3e) from Gadget
> Factory.  Has anyone tried to make such an extended-resolution TDC using
> this type of FPGA platform? Any opinions on whether it can be done?
>
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