[time-nuts] FE-5680A programming connector pinout

[John Beale]

 > http://www.rhodiatoce.com/pics/time-nuts/FE-5680A_annotated.jpg

Excellent work!  I look forward to any further info.

Great picture with the pins and some parts labelled. By the way, if you 
want you could add the frequencies going into and out of the Xilinx 
XC9572XL CPLD part:

Pin 64: 60 MHz in from VCXO
Pin 1: 20 MHz out to AD9832 DDS chip
Pin 22: 30 MHz out
Pin 49: 10 MHz out to sine shaping network

See also:
https://plus.google.com/photos/109928236040342205185/albums/5680473650837554113/5685304134718133138

It might clarify things to point out the 60 MHz through-hole crystal pins 
visible immediately below the MMBV432 varactor diode.

Knowing that's the varactor, and looking at the circuit I'm guessing the 
VCXO tuning voltage must pass through the 10K resistor next to mini-coax 
connector J8 (then past the bypass cap, through the 1.0 uH inductor, to the 
diode).  That 10k connects through a 1k to pin 8 (output 3) of the TLC27M4B 
quad opamp on the other side of the board, near the 60 MHz xtal. Hmm.... 
sure enough: at startup, pin 8 swings between 0 and 11.9V, before the unit 
locks, which in my case happens at 7.3 Volts.  (The opamp is powered from a 
13.16V supply, output swings typ. 1.3V below the + rail.)

Just for fun, here's a plot of the VCXO tuning voltage at startup:
https://picasaweb.google.com/109928236040342205185/FE5680A#5704421825887557874